NCP5425_06 ONSEMI [ON Semiconductor], NCP5425_06 Datasheet - Page 21

• Manufacturer Part Number: NCP5425_06
• Description: Dual Synchronous Buck Controller
• Manufacturer: ONSEMI [ON Semiconductor]

EMI MANAGEMENT
at high frequency, switching regulators generate noise
during normal operation. When designing for compliance
with EMI/EMC regulations, additional components may be
necessary to reduce noise emissions. These components are
not required for regulator operation and experimental results
may allow them to be eliminated. The input filter inductor
may not be required because bulk filter and bypass
capacitors, as well as other loads located on the board will
tend to reduce regulator di/dt effects on the circuit board and
input power supply. Placement of the power components to
minimize routing distance will also help to reduce
emissions.
LAYOUT GUIDELINES
board, the following checklist should be used to ensure
proper operation of the NCP5425.
As a consequence of large currents being turned on and off
When laying out a buck regulator on a printed circuit
1. Rapid changes in voltage across parasitic capacitors
2. Keep high currents out of sensitive ground
3. Avoid ground loops as they pick up noise. Use star
4. For high power buck regulators on double−sided
5. Even though double sided PCB’s are usually
and abrupt changes in current in parasitic inductors
are major concerns.
connections.
or single point grounding.
PCB’s a single ground plane (usually the bottom)
is recommended.
sufficient for a good layout, four−layer PCB’s are
http://onsemi.com
NCP5425
21
10. Place the output capacitors as close to the load as
12. Connect the filter components of pins R
13. Place the V
14. Place the R
15. Assign the output with lower duty cycle to
11. Place the COMP capacitor as close as possible to
6. Keep the inductor switching node small by placing
7. The MOSFET gate traces to the IC must be short,
8. Use fewer, but larger output capacitors, keep the
9. Place the switching MOSFET as close to the input
the optimum approach to reducing susceptibility to
noise. Use the two internal layers as the power and
GND planes, the top layer for power connections
and component vias, and the bottom layers for the
noise sensitive traces.
the output inductor, switching and synchronous
FETs close together.
straight, and wide as possible.
capacitors clustered, and use multiple layer traces
with wide, thick copper to keep the parasitic
resistance low.
capacitors as possible.
possible.
the COMP pin.
V
trace, and connect this local GND trace to the
output capacitor GND.
to the IC.
R
channel 2, which has inherently better noise
immunity.
OSC
OUT
, and COMP, to the GND pin with a single
pin.
CC
OSC
bypass capacitors as close as possible
resistor as close as possible to the
OSC,
V
FB
,