NCP5422A_06 ONSEMI [ON Semiconductor], NCP5422A_06 Datasheet - Page 12

• Manufacturer Part Number: NCP5422A_06
• Description: Dual Out−of−Phase Synchronous Buck Controller with Current Limit
• Manufacturer: ONSEMI [ON Semiconductor]

therefore:
where:
that at least 40 dB attenuation is obtained at the regulator
switching frequency. The LC filter is a double−pole network
with a slope of −2.0, a roll−off rate of −40 dB/dec, and a
corner frequency:
where:
FET Basics
two reasons: 1) Its very high input impedance; and 2) Its very
fast switching times. The electrical characteristics of a
MOSFET are considered to be those of a perfect switch.
Control and drive circuitry power is therefore reduced.
Because the input impedance is so high, it is voltage driven.
The input of the MOSFET acts as if it were a small capacitor,
which the driving circuit must charge at turn on. The lower
the drive impedance, the higher the rate of rise of V
the faster the turn−on time. Power dissipation in the
switching MOSFET consists of 1) conduction losses, 2)
leakage losses, 3) turn−on switching losses, 4) turn−off
switching losses, and 5) gate−transitions losses. The latter
three losses are proportional to frequency.
Static Drain−To−Source On−Resistance (R
affects regulator efficiency and FET thermal management
requirements. The On−Resistance determines the amount of
current a FET can handle without excessive power
dissipation that may cause overheating and potentially
catastrophic failure. As the drain current rises, especially
above the continuous rating, the On−Resistance also
increases. Its positive temperature coefficient is between
+0.6%/°C and +0.85%/°C. The higher the On−Resistance
the larger the conduction loss is. Additionally, the FET gate
charge should be low in order to minimize switching losses
and reduce power dissipation.
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the FET gates
The minimum inductance value for the input inductor is
L
DV = voltage seen by the input inductor during a full load
(dI/dt)
The designer must select the LC filter pole frequency so
L = input inductor;
C = input capacitor(s).
The use of the MOSFET as a power switch is propelled by
The most important aspect of FET performance is the
Both logic level and standard FETs can be used.
Voltage applied to the FET gates depends on the
IN
= input inductor value;
swing;
MAX
SELECTION OF THE POWER FETS
= maximum allowable input current slew rate.
L IN +
f C +
(dI dt) MAX
2p
DV
1
LC
DS(ON)
NCP5422A, NCP5423
), which
GS
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, and
12
will be driven rail−to−rail due to overshoot caused by the
capacitive load they present to the controller IC.
Selection of the Switching (Upper) FET
in the FET switch does not cause the power component to
exceed it’s maximum rating.
determined by the following formula:
where:
switching MOSFET conduction losses can be calculated:
where:
MOSFET switch−on and switch−off and can be determined
by using the following formula:
where:
then be calculated as:
where:
known, the maximum FET switch junction temperature can
be calculated:
P HFET(TOTAL) + P RMS(H) ) P SWH(ON) ) P SWH(OFF)
The designer must ensure that the total power dissipation
The maximum RMS current through the switch can be
I RMS(H) +
I
I
I
D = duty cycle.
Once the RMS current through the switch is known, the
P
I
R
The upper MOSFET switching losses are caused during
P
P
V
I
t
t
T = 1/f
The total power dissipation in the switching MOSFET can
P
P
P
P
Once the total power dissipation in the switching FET is
RISE
FALL
RMS(H)
L(PEAK)
L(VALLEY)
RMS(H)
OUT
RMS(H)
SWH(ON)
SWH(OFF)
HFET(TOTAL)
RMS(H)
SWH(ON)
SWH(OFF)
DS(ON)
IN
= input voltage;
= load current;
= MOSFET rise time (from FET manufacturer’s
= MOSFET fall time (from FET manufacturer’s
SW
switching characteristics performance curve);
T J + T A ) [P HFET(TOTAL)
P SWH + P SWH(ON) ) P SWH(OFF)
= maximum switching MOSFET RMS current;
= maximum switching MOSFET RMS current;
switching characteristics performance curve);
P RMS(H) + I RMS(H) 2
= switching MOSFET conduction losses;
= FET drain−to−source on−resistance
= upper MOSFET switch conduction Losses;
= inductor peak current;
= upper MOSFET switch−on losses;
= period.
= upper MOSFET switch−on losses;
= upper MOSFET switch−off losses;
= upper MOSFET switch−off losses;
= inductor valley current;
= total switching (upper) MOSFET losses;
+
I L(PEAK) 2 ) (I L(PEAK)
) I L(VALLEY) 2
V IN
I OUT
6T
(t RISE ) t FALL )
D
3
R DS(ON)
R qJA ]
I L(VALLEY) )