ADP3178JR AD [Analog Devices], ADP3178JR Datasheet - Page 6

• Manufacturer Part Number: ADP3178JR
• Description: 4-Bit Programmable Synchronous Buck Controllers
• Manufacturer: AD [Analog Devices]

ADP3158/ADP3178
The linear regulator controllers have been designed so that they
remain active even when the switching controller is in UVLO mode
to ensure that the output voltages of the linear regulators will track
the 3.3 V supply as required by Intel design specifications. By
diode ORing the VCC input of the IC to the 5 VSB and 12 V
supplies as shown in Figure 3, the switching output will be disabled
in standby mode, but the linear regulators will begin conducting
once VCC rises above about 1 V. During start-up the linear out-
puts will track the 3.3 V supply up until they reach their respective
regulation points, regardless of the state of the 12 V supply. Once
the 12 V supply has exceeded the 5 VSB supply by more than a
diode drop, the controller IC will track the 12 V supply. Once the
12 V supply has risen above the UVLO value, the switching regula-
tor will begin its start-up sequence.
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
2.5V, 2A
V
LR1
10k
R2
C15
1 F
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Table I. Output Voltage vs. VID Code
100 F
FROM CPU
Q1
C1
3.3V
+
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
C2
68pF
C10
1nF
1
2
3
4
5
6
7
8
VID0
VID1
VID2
VID3
LRFB1
LRDRV1
CS–
CS+
ADP3158/
ADP3178
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
U1
220
R4
LRDRV2
LRFB2
COMP
DRVH
DRVL
GND
VCC
220
CT
R3
150pF
16
15
14
13
12
11
10
9
C3
V
1.30 V
1.35 V
1.40 V
1.45 V
1.50 V
1.55 V
1.60 V
1.65 V
1.70 V
1.75 V
1.80 V
1.85 V
1.90 V
1.95 V
2.00 V
2.05 V
OUT(NOM)
10.5k
R
B
R
78.7k
A
C
2.7nF
OC
APPLICATION INFORMATION
Specifications for a Design Example
The design parameters for a typical 750 MHz Pentium III appli-
cation (shown in Figure 3) are as follows:
The above requirements correspond to Intel’s published power
supply requirements based on VRM 8.4 guidelines.
+
Input Voltage: (V
Auxiliary Input: (V
Output Voltage (V
Maximum Output Current (I
Minimum Output Current (I
Static tolerance of the supply voltage for the processor core
( V
Transient tolerance (for less than 2 s) of the supply voltage
for the processor core when the load changes between the
minimum and maximum values with a di/dt of 20 A/ s
( V
Input current di/dt when the load changes between the mini-
mum and maximum values < 0.1 A/ s.
C6
1 F
C11
68pF
O
O(TRANSIENT)
) = +40 mV (–80 mV) = 120 mV
3.3V
Q4
Q2
+
Q3
C2
100 F
C12
1 F
) = +80 mV (–130 mV) = 210 mV
+
C7
22 F
IN
1.7 H
VID
R11
10k
CC
) = 5 V
L1
V
1.8V,
2A
) = 12 V
) = 1.7 V
LR2
+
4m
C8
1000 F
R12
O(MIN)
O(MAX)
C17 C18 C19 C20 C21
+
+
24m
1000 F
) = 1 A
C9
1000 F
) = 15 A
MBR052LT1
MBR052LT1
+
SUB45N03-13L
SUB75N03-07
(EACH)
1 H
L2
D2
D3
+
5
+
+
12V
5V STANDBY
5V
VCC CORE
1.30V TO
2.05V
15A