ADP3178JR AD [Analog Devices], ADP3178JR Datasheet - Page 10

• Manufacturer Part Number: ADP3178JR
• Description: 4-Bit Programmable Synchronous Buck Controllers
• Manufacturer: AD [Analog Devices]

ADP3158/ADP3178
Note that there is a trade-off between converter efficiency and
cost. Larger MOSFETs reduce the conduction losses and allow
higher efficiency, but increase the system cost. If efficiency is not a
major concern, a Vishay-Siliconix SUB45N03-13L (R
10 m
Vishay-Siliconix SUB75N03-07 (R
10 m worst-case) for the low-side are good choices.
The high-side MOSFET dissipation is:
where the second term represents the turn-off loss of the
MOSFET. In the second term, Q
removed from the gate for turn-off and I
From the data sheet, Q
provided by the ADP3159 is about 1 A.
The low-side MOSFET dissipation is:
Note that there are no switching losses in the low-side MOSFET.
Surface mount MOSFETs are preferred in CPU core converter
applications due to their ability to be handled by automatic
assembly equipment. The TO-263 package offers the power
handling of a TO-220 in a surface-mount package. However,
this package still needs adequate copper area on the PCB to
help move the heat away from the package.
The junction temperature for a given area of 2-ounce copper
can be approximated using:
assuming:
For 1 in
ambient temperature of 50 C:
All of the above-calculated junction temperatures are safely
below the 175 C maximum specified junction temperature of
the selected MOSFETs.
C
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to V
maximum output current. To prevent large voltage transients, a
P
P
DHSF
DHSF
IN
JA
JA
JA
Selection and Input Current di/dt Reduction
T
P
P
= 45 C/W for 0.5 in
= 36 C/W for 1 in
= 28 C/W for 2 in
DLSF
DLSF
J
I
8 8
nominal, 16 m worst-case) for the high-side and a
2
RMSHSF
.
of copper area attached to each transistor and an
T
T
A
JHSF
JLSF
J
2
A
10 8
I
RMSLSF
2
16
.
= (36 C/W
OUT
= (36 C/W
P
R
D
m
A
DS ON
/V
2
(
2
IN
T
G
5
)
10
2
A
2
R
V
and an amplitude of one-half of the
is 70 nC and the gate drive current
2
DS ON
V
m
IN
15
(
1.08 W) + 50 C = 89 C
1.48 W) + 50 C = 103 C
A
I
)
L PEAK
1 08
G
2 1
(
.
70
is the gate charge to be
2
DS(ON)
nC
A
)
W
I
G
G
Q
195
is the gate current.
G
= 6 m
kHz
f
MIN
nominal,
1 75
.
DS(ON)
W
(19)
(20)
(21)
=
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by:
For a ZA-type capacitor with 1000 F capacitance and 6.3 V
voltage rating, the ESR is 24 m and the maximum allowable
ripple current at 100 kHz is 2 A. At 105 C, at least four such
capacitors must be connected in parallel to handle the calculated
ripple current. At 50 C ambient, however, a higher ripple cur-
rent can be tolerated, so three capacitors in parallel are adequate.
The ripple voltage across the three paralleled capacitors is:
V
V
To further reduce the effect of the ripple voltage on the system
supply voltage bus, and to reduce the input-current di/dt to
below the recommended maximum of 0.1 A/ms, an additional
small inductor (L > 1 H @ 10 A) should be inserted between
the converter and the supply bus.
Feedback Compensation for Active Voltage Positioning
Optimized compensation of the ADP3158 and ADP3178 allows
the best possible containment of the peak-to-peak output voltage
deviation. Any practical switching power converter is inherently
limited by the inductor in its output current slew rate to a value
much less than the slew rate of the load. Therefore, any sudden
change of load current will initially flow through the output capaci-
tors, and this will produce an output voltage deviation equal to the
ESR of the output capacitor array times the load current change.
C IN RIPPLE
C IN RIPPLE
(
(
)
)
I
C RMS
15
(
2
TEK RUN: 200kS/s SAMPLE
A
)
15
CH1
I
0 36 0 36
O
.
A
I
O
ESR
– .
100mV
24
D
n
HSF
C IN
C
3
m
(
2
)
D
3 1000
n
CH2
HSF
7 2
C
.
TRIG'D
C
2
D
A
IN
M 250 s
HSF
36
F
%
f
MAX
195
kHz
CH2
129
680mV
mV
(23)
(22)