NCP1650_05 ONSEMI [ON Semiconductor], NCP1650_05 Datasheet - Page 21

• Manufacturer Part Number: NCP1650_05
• Description: Power Factor Controller
• Manufacturer: ONSEMI [ON Semiconductor]

Current Sense Amplifier
with a differential input. It consists of a differential input
stage, a high frequency current mirror and a low frequency
current mirror, for a total of three current outputs. Two of
them (AC Error Amplifier and Power Multiplier) are
generated from the
filtered to resemble the average value of the input current.
The third output is the instantaneous inductor current and is
generated from the
of the PWM.
configuration. The voltage developed across the current
shunt is sensed at the Is− input. The amplifier input is
designed for negative going voltages only; the power stage
should resemble the configuration of the circuit in Figure 39.
between the shunt resistor and this input, due to the low
impedance of this amplifier. Any series resistance due to a
filter, will create an offset of:
which will add a negative offset to the current signal. The
effect of this is that current information will be lost when the
current signal is below the offset level. This will be a
problem mainly at light loads and near the zero crossings.
into a current (i
of the i
replica of the instantaneous current in the inductor. The
conversion of the current sense signal to current i
PWM input where it is added to the AC error amp signal and
the ramp compensation signal.
to a buffer amplifier. This signal is the result of i
The current sense amplifier is a wide bandwidth amplifier
The input to the current sense amplifier is a common base
Caution should be exercised when designing a filter
The voltage across the current shunt resistor is converted
The PWM output sends that information directly to the
The other output of the i
1 k
1
current mirror is a high frequency signal that is a
Figure 38. Current Sense Amplifier
1 k
12
CURRENT
MIRROR
1
V OS + 50 mA
), which drives a current mirror. The output
i
1
I
S−
i
i
2
1
mirror, and their waveforms have been
i 1 + Vi s− 1 k
i
15 k
mirror which directly feeds the input
1
11
1
i
1
PWM
C
mirror provides a voltage signal
I
avg fltr
11
+
−
R external
10
CURRENT
MIRROR
i
I
2
R
avg
10
i
AC Error
1
2
Pwr Mult
1
Amp
dropped
is:
http://onsemi.com
i
2
NCP1650
21
across an internal 15 kW resistor, and filtered by a capacitor
at pin 11. This signal, when properly filtered, will be the 2x
line frequency fullwave rectified sinewave. The filter pole
on pin 11 should be far enough below the switching
frequency to remove most of the high frequency component,
but high enough above the line frequency so as not to cause
significant distortion to the input fullwave rectified
sinewave waveform.
frequency, a 10 kHz pole will normally work well. The
capacitor at pin 11 can be calculated knowing the desired
pole frequency by the equation:
Where:
C
f = pole frequency (kHz)
or, for a 10 kHz pole, C
value of the resistor at pin 10. The value of R10 affects the
operation of the AC error amplifier as well as the maximum
power level. Power multiplier gain calculations are included
in the description of that circuit.
PWM and Logic
comparator, an RS flip−flop (latch) and an OR gate. The
latch has two Set inputs and one Reset input. The Reset input
is dominant over the PWM Set input, but the Overshoot
Comparator Set input is dominant over the Reset input. The
two Set Inputs are effectively OR’ed together although their
dominance varies.
scheme based on a fixed frequency oscillator. The oscillator
outputs a ramp waveform as well as a pulse which is
coincident with the falling edge of the ramp. The pulse is fed
into the PWM latch and AND gate that follows. During the
pulse, the latch is reset, and the output drive is in it’s low state.
and the power switch begins conduction. The instantaneous
inductor current is summed with the AC error amplifier
voltage and the ramp compensation signal to create a
complex waveform that is compared to the 4.0 volt reference
signal on the inverting input to the PWM comparator. When
the signal at the non−inverting input to the PWM comparator
exceeds 4.0 volts, the output of the PWM comparator
changes to a high state which drives one of the Set inputs to
the latch and turns the power switch off until the next
oscillator cycle. Figure 40 shows the relationships of the
oscillator and logic signals.
cycle−by−cycle PWM operation. The UVLO circuit feeds
directly into the AND gate and will inhibit operation until
the input voltage is in a valid range. The Overshoot
11
For a 100 kHz switching frequency and a 60 Hz line
The gain of the low frequency current buffer is set by the
The PWM and logic circuits are comprised of a PWM
The NCP1650 uses a standard Pulse Width Modulation
On the falling edge of the pulse, the output drive goes high
There are two override signals to the normal
= Pin 11 capacitance (nF)
C 11 + 10.5
11
would be 1.0 nF.
f