S-8233BBFT SII [Seiko Instruments Inc], S-8233BBFT Datasheet - Page 13

• Manufacturer Part Number: S-8233BBFT
• Description: BATTERY PROTECTION IC (FOR A 3-SERIAL-CELL PACK)
• Manufacturer: SII [Seiko Instruments Inc]

Rev.4.2
Operation
Normal condition
Over current condition
Over charge condition
The over current condition returns to the normal condition when the load is released and the impedance
This IC is provided with the three over current detection levels (V
current detection delay time (t
If the discharging current becomes equal to or higher than a specified value (the VMP terminal voltage is
equal to or higher than the over current detection voltage) during discharging under normal condition and
it continues for the over current detection delay time (t
discharging. This condition is called an over current condition. The VMP and VCC terminals are shorted
by the R
When the discharging FET is off and a load is connected, the VMP terminal voltage equals the V
potential.
If one of the battery voltages becomes higher than the over charge detection voltage (V
charging under normal condition and it continues for the over charge detection delay time (t
the charging FET turns off to stop charging. This condition is called the over charge condition. The 'H'
level signal is output to the conditioning terminal corresponding to the battery which exceeds the over
charge detection voltage until the battery becomes equal to lower than the over charge release voltage
(V
be limited by inserting R11, R12 and R13 resistors (see Figure 9 for a connection example). The VMP
and VCC terminals are shorted by the R
The over charge condition is released in two cases:
Remark Refer to “Battery Protection IC Connection Example”.
This IC monitors the voltages of the three serially-connected batteries and the discharge current to control
charging and discharging. If the voltages of all the three batteries are in the range from the over
discharge detection voltage (V
through the batteries becomes equal or lower than a specified value (the VMP terminal voltage is equal or
lower than over current detection voltage 1), the charging and discharging FETs turn on. In this condition,
charging and discharging can be carried out freely. This condition is called the normal condition. In this
condition, the VMP and VCC terminals are shorted by the R
between the EB- and EB+ terminals (see Figure 9 for a connection example) is 100 MΩ or higher. When
the load is released, the VMP terminal, which and the VCC terminal are shorted with the R
goes back to the V
detection voltage 1 (V
terminal is fixed at the 'L' level and over current detection 1 is inhibited) and returns to the normal
condition.
1) The battery voltage which exceeded the over charge detection voltage (V
2) If the battery voltage which exceeded the over charge detection voltage (V
CD
The release mechanism is as follows: the discharge current flows through an internal parasitic diode
of the charging FET immediately after a load is installed and discharging starts, and the VMP terminal
voltage decreases by about 0.6 V from the VCC terminal voltage momentarily. The IC detects this
voltage (over current detection voltage 1 or higher), releases the over charge condition and returns to
the normal condition.
_00
). The battery can be discharged by connecting an Nch FET externally. The discharging current can
charge release voltage (V
the over charge release voltage (V
starts, the charging FET turns on and the normal condition returns.
VCM
resistor at this time. The charging FET turns off.
CC
potential. The IC detects that the VMP terminal potential returns to over current
IOV1
) or lower (or the over current detection voltage 2 (V
IOV1
CD
DD
), the charging FET turns on and the normal condition returns.
) to the over charge detection voltage (V
,t
IOV2
BATTERY PROTECTION IC FOR 3-SERIAl-CELL PACK
and t
Seiko Instruments Inc.
CD
VCM
), but the charger is removed, a load is placed, and discharging
IOV3
resistor under the over charge condition.
) corresponding to each over current detection level.
IOV
) or longer, the discharging FET turns off to stop
VCM
resistor.
IOV1
,V
IOV2
CU
and V
), and the current flowing
IOV2
CU
CU
) falls below the over
IOV3
) or lower if the COVT
) is equal or higher than
) and the three over
S-8233B Series
CU
) during
VCM
CU
) or longer,
resistor,
SS
13