UC384XBD MOTOROLA [Motorola, Inc], UC384XBD Datasheet - Page 9

• Manufacturer Part Number: UC384XBD
• Description: HIGH PERFORMANCE CURRENT MODE CONTROLLERS
• Manufacturer: MOTOROLA [Motorola, Inc]

Undervoltage Lockout
incorporated to guarantee that the IC is fully functional before
the output stage is enabled. The positive power supply
terminal (V CC ) and the reference output (V ref ) are each
monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The V CC comparator
upper and lower thresholds are 16 V/10 V for the UCX844B,
and 8.4 V/7.6 V for the UCX845B. The V ref comparator upper
and lower thresholds are 3.6 V/3.4 V. The large hysteresis
and low startup current of the UCX844B makes it ideally
suited in off–line converter applications where efficient
bootstrap startup techniques are required (Figure 29). The
UCX845B is intended for lower voltage dc–to–dc converter
applications. A 36 V zener is connected as a shunt regulator
from V CC to ground. Its purpose is to protect the IC from
excessive voltage that can occur during system startup. The
minimum operating voltage for the UCX844B is 11 V and 8.2
V for the UCX845B.
Output
that was specifically designed for direct drive of power
MOSFETs. It is capable of up to 1.0 A peak drive current and
has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull–down resistor.
pins for V C (output supply) and Power Ground. Proper
implementation will significantly reduce the level of switching
transient noise imposed on the control circuitry. This
becomes particularly useful when reducing the I pk(max) clamp
level. The separate V C supply input allows the designer
The diode clamp is required if the Sync amplitude is large enough to cause
the bottom side of C T to go more than 300 mV below ground.
External
Sync
Input
MOTOROLA ANALOG IC DEVICE DATA
Two undervoltage lockout comparators have been
These devices contain a single totem pole output stage
The SO–14 surface mount package provides separate
Figure 17. External Clock Synchronization
0.01
C T
R T
47
V ref
8(14)
4(7)
2(3)
1(1)
EA
R
R
+
Bias
Osc
UC3844B, 45B UC2844B, 45B
2R
R
5(9)
added flexibility in tailoring the drive voltage independent of
V CC . A zener clamp is typically connected to this input when
driving power MOSFETs in systems where V CC is greater
than 20 V. Figure 22 shows proper power and control ground
connections in a current–sensing power MOSFET
application.
Reference
tolerance at T J = 25 C on the UC284XB, and 2.0% on the
UC384XB. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has
short–circuit protection and is capable of providing in excess
of 20 mA for powering additional control system circuitry.
Design Considerations
wire–wrap or plug–in prototype boards. High frequency
circuit layout techniques are imperative to prevent
pulse–width jitter. This is usually caused by excessive noise
pick–up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low–current signal and
high–current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 F) connected directly to V CC , V C ,
and V ref may be required depending upon circuit layout. This
provides a low impedance path for filtering the high frequency
noise. All high current loops should be kept as short as
possible using heavy copper runs to minimize radiated EMI.
The Error Amp compensation circuitry and the converter
output voltage divider should be located close to the IC and
as far as possible from the power switch and other
noise–generating components.
f
R A
R B
+
C
The 5.0 V bandgap reference is trimmed to
Do not attempt to construct the converter on
6
5
2
Figure 18. External Duty Cycle Clamp and
(R A
8
)
5.0k
5.0k
5.0k
1
1.44
2R B )C
Multi–Unit Synchronization
MC1455
R
S
Q
4
D (max)
3
7
+
R A
)
R A
8(14)
4(7)
2(3)
1(1)
To Additional
UCX84XBs
2R B
R
R
EA
+
Osc
Bias
2R
5(9)
1.0%
R
9