NCP1294ED16 ONSEMI [ON Semiconductor], NCP1294ED16 Datasheet
NCP1294ED16
Related parts for NCP1294ED16
NCP1294ED16 Summary of contents
Page 1
... Assembly Location WL Wafer Lot YY Year WW Work Week = Pb−Free Package G ORDERING INFORMATION Device Package NCP1294ED16 SOIC−16 NCP1294ED16G SOIC−16 (Pb−Free) NCP1294EDR16 SOIC−16 2500 Tape & Reel NCP1294EDR16G SOIC−16 (Pb−Free) NCP1294EDTB16G TSSOP−16 (Pb−Free) NCP1294EDTB16R2G TSSOP−16 (Pb−Free) † ...
Page 2
NCP1294 Figure 1. Application Diagram, 36 V− 5.0 V/5.0 A Converter http://onsemi.com 2 ...
Page 3
MAXIMUM RATINGS Operating Junction Temperature Lead Temperature Soldering: Storage Temperature Range ESD (Human Body Model) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions ...
Page 4
ELECTRICAL CHARACTERISTICS (−40°C < 390 pF; unless otherwise specified Characteristic Reference Voltage Total Accuracy Line Regulation Load Regulation Noise Voltage Op Life Shift Fault Voltage V Voltage REF(OK) V Hysteresis REF(OK) ...
Page 5
ELECTRICAL CHARACTERISTICS (−40°C < 390 pF; unless otherwise specified Characteristic Gate Driver High Saturation Voltage Low Saturation Voltage High Voltage Clamp Output Current Output UVL Leakage Rise Time Fall Time Max ...
Page 6
PACKAGE PIN DESCRIPTION Package Pin Pin # Symbol 1 GATE External power switch driver with 1.0 A peak capability. Rail to rail output occurs when the capacitive load is between 470 pF and 10 nF Current sense comparator ...
Page 7
UVL − ENABLE + − UV Lockout Start/Stop SYNC 2 1.0 V Trip Points V 3 (1.263 V) − EAMP − COMP Soft−Start Clamp FF ...
Page 8
THEORY OF OPERATION Feed Forward Voltage Mode Control In conventional voltage mode control, the ramp signal has fixed rising and falling slope. The feedback signal is derived solely from the output voltage. Consequently, voltage mode control has inferior line regulation ...
Page 9
Soft−Start can be programmed through a capacitance connected to the SS pin. The constant charging current to the SS pin (typ). The V (ok) comparator monitors the 3 REF output and latches a ...
Page 10
Figure 8. The SYNC Pin Generates a Sync Pulse at the Beginning of Each Switching Cycle. CH2: GATE Pin, CH3 CH4: SYNC Pin T T Figure 9. Operation with External Sync. CH2: SYNC Pin, CH3: GATE Pin, ...
Page 11
500 400 300 200 100 0.0001 0.001 C (mF) T Figure 10. Typical Performance Characteristics, Oscillator Frequency vs. C that during ...
Page 12
G K −T− SEATING PLANE 0.25 (0.010 PACKAGE THERMAL DATA Parameter R qJC R qJA PACKAGE DIMENSIONS SOIC−16 D SUFFIX CASE 751B−05 ISSUE K −B− 0.25 ...
Page 13
K 16X 0.10 (0.004) 0.15 (0.006 L PIN 1 IDENT. 1 0.15 (0.006 −V− C 0.10 (0.004) −T− SEATING D PLANE 16X 0.36 ON Semiconductor and are registered trademarks of ...