XC17128EPCG20C XILINX [Xilinx, Inc], XC17128EPCG20C Datasheet
XC17128EPCG20C
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XC17128EPCG20C Summary of contents
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R DS027 (v3.5) June 25, 2008 Features • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGAs • Simple interface to the FPGA; requires only one user I/O pin • Cascadable for storing longer or multiple ...
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R Pin Description DATA Data output high-impedance state when either are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. CLK ...
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R Pinout Diagrams Pinout Diagrams PC44 PC44 Top View Top View ...
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R Xilinx FPGAs and Compatible PROMs Configuration Device Bits XC4003E 53,984 XC4005E 95,008 XC4006E 119,840 XC4008E 147,552 XC4010E 178,144 XC4013E 247,968 XC4020E 329,312 XC4025E 422,176 XC4002XL 61,100 XC4005XL 151,960 XC4010XL 283,424 XC4013XL/XLA 393,632 XC4020XL/XLA 521,880 XC4028XL/XLA 668,184 XC4028EX 668,184 XC4036EX/XL/XLA ...
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R FPGA Master Serial Mode Summary The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up command, depending ...
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R X-Ref Target - Figure FPGA (1) MODES RESET RESET CCLK DONE (Low Resets the Address Pointer) CCLK (Output OUT (Output) Notes: 1. For mode pin connections, refer to the appropriate FPGA data ...
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R XC1701, XC1736E, XC1765E, XC17128E and XC17256E Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage relative to GND PP V Input voltage relative to GND IN V Voltage applied to High-Z output TS T ...
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R XC1704L, XC1702L, XC1701L, XC17512L, XC1765EL, XC17128EL and XC17256EL Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Supply voltage relative to GND PP V Input voltage relative to GND IN V Voltage applied to High-Z output ...
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R AC Characteristics Over Operating Condition CE RESET/OE CLK T CE DATA Symbol Description data delay data delay CE T CLK to data delay CAC data float delay ...
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R AC Characteristics Over Operating Condition When Cascading RESET/OE CE CLK DATA First (First PROM) Bit T OOE CEO (First PROM) CE (Cascaded PROM) DATA (Cascaded PROM) Symbol Description (2,3) T CLK to data float delay CDF (3) T CLK ...
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... DS027 (v3.5) June 25, 2008 Product Specification XC1700E, XC1700EL, and XC1700L Series Configuration PROMs XC1701L PC20 C (1) XC17128EPD8C XC17256EPD8C XC17128EPDG8C XC17256EPDG8C XC17128EVO8C XC17256EVO8C XC17128EVOG8C XC17256EPC20C XC17128EPC20C XC17256EPCG20C XC17128EPCG20C XC17128EPD8I XC17128EVO8I XC17256EPD8I XC17128EPC20I XC17256EVO8I XC17256EPC20I XC17128ELPD8C XC17256ELPD8C XC17128ELVO8C XC17256ELVO8C XC17128ELPC20C XC17256ELPC20C XC17128ELPD8I XC17256ELPD8I XC17128ELVO8I ...
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R Marking Information Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as ...
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R • Changed pinout diagrams to include Pb-free packages on 06/13/05 3.3 • Deleted T • Added VOG8 and PCG20 to XC17256EPCG20 to "Marking Information," page • Added Pb-free packages to 07/09/07 3.4 • Note added to • Under Characteristics ...