AT17C002 ATMEL [ATMEL Corporation], AT17C002 Datasheet - Page 16
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AT17C002
Manufacturer Part Number
AT17C002
Description
FPGA Configuration EEPROM Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT17C002.pdf
(19 pages)
20J – PLCC
16
0.51(0.020)MAX
Notes:
45˚ MAX (3X)
R
AT17C/LV002
1.14(0.045) X 45˚
2325 Orchard Parkway
San Jose, CA 95131
B
1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
TITLE
D1
D
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
PIN NO. 1
IDENTIFIER
e
E1
E
1.14(0.045) X 45˚
SYMBOL
D2/E2
A
A1
A2
D
D1
E
E1
B
B1
e
4.191
2.286
9.779
8.890
9.779
8.890
7.366
0.660
0.330
0.508
COMMON DIMENSIONS
MIN
(Unit of Measure = mm)
A
1.270 TYP
B1
NOM
–
–
–
–
–
–
–
–
–
–
A2
A1
0.318(0.0125)
0.191(0.0075)
DRAWING NO.
D2/E2
10.033
10.033
4.572
3.048
9.042
9.042
8.382
0.813
0.533
MAX
–
20J
Note 2
Note 2
NOTE
10/04/01
2281D–12/01
REV.
B