COP424C NSC [National Semiconductor], COP424C Datasheet - Page 10

• Manufacturer Part Number: COP424C
• Description: Single-Chip 1k and 2k CMOS Microcontrollers
• Manufacturer: NSC [National Semiconductor]

Functional Description
INITIALIZATION
The internal reset logic will initialize the device upon power-
up if the power supply rise time is less than 1 ms and if the
operating frequency at CKI is greater than 32 kHz other-
wise the external RC network shown in Figure 7 must be
connected to the RESET pin (the conditions in Figure 7
must be met) The RESET pin is configured as a Schmitt
trigger input If not used it should be connected to V
Initialization will occur whenever a logic ‘‘0’’ is applied to the
RESET input providing it stays low for at least three instruc-
tion cycle times
Note If CKI clock is less than 32 kHz the internal reset logic (option
Upon initialization the PC register is cleared to 0 (ROM ad-
dress 0) and the A B C D EN IL T and G registers are
cleared The SKL latch is set thus enabling SK as a clock
output Data Memory (RAM) is not cleared upon initializa-
tion The first instruction at address 0 must be a CLRA
(clear A register)
2 096 MHz
4 0 MHz
455 kHz
Crystal
32 kHz
Value
29
e
1) MUST be disabled and the external RC circuit must be used
FIGURE 7 Power-Up Circuit
220k
Crystal or Resonator
R1
5k
2k
1k
Component Values
20M
10M
R2
1M
1M
C1(pF)
(Continued)
30
80
30
30
FIGURE 8 Oscillator Component Values
TL DD 5259–8
C2(pF)
6–36
6–36
6–36
40
CC
10
TIMER
The timer can be operated as a time-base counter
The instruction cycle frequency generated from CKI passes
through a 2-bit divide-by-4 prescaler The output of this pre-
scaler increments the 8-bit T counter thus providing a 10-bit
timer The pre-scaler is cleared during execution of a CAMT
instruction and on reset
For example using a 4 MHz crystal with a divide-by-16 op-
tion the instruction cycle frequency of 250 kHz increments
the 10-bit timer every 4
detecting overflow accurate timeouts between 16
(4 counts) and 4 096 ms (1024 counts) are possible Longer
timeouts can be achieved by accumulating under software
control multiple overflows
HALT MODE
The COP444C 445C 424C 425C 426C is a FULLY STAT-
IC circuit therefore the user may stop the system oscillator
at any time to halt the chip The chip may also be halted by
the HALT instruction or by forcing CKO high when it is
mask-programmed as an HALT I O port Once in the HALT
mode the internal circuitry does not receive any clock sig-
nal and is therefore frozen in the exact state it was in when
halted All information is retained until continuing The chip
may be awakened by one of two different methods
Note 15k
30k
60k
Continue function by forcing CKO low if it mask-pro-
grammed as an HALT I O port the system clock is re-
enabled and the circuit continues to operate from the
point where it was stopped
Restart by forcing the RESET pin low (see Initializa-
tion)
R
50 pF
RC Controlled Oscillator (
s
R
s
s
C
s
150k
150 pF
100 pF
82 pF
C
s By presetting the counter and
12– 24 s
5 – 11 s
Cycle
Time
g
5% R
g
5% C)
2 4– 4 5V
t
TL DD 5259 – 9
V
4 5V
CC
s