AT45DB321C-RI ATMEL [ATMEL Corporation], AT45DB321C-RI Datasheet - Page 7

• Manufacturer Part Number: AT45DB321C-RI
• Description: 32 MEGABIT 2.7 VOLT DATAFLASH
• Manufacturer: ATMEL [ATMEL Corporation]

AT45DB321C [Preliminary]
that specify the page in main memory to be rewritten and 10 don’t care bits. When a low-
to-high transition occurs on the CS pin, the part will first transfer data from the page in
main memory to a buffer and then program the data from the buffer back into same
page of main memory. The operation is internally self-timed and should take place in a
maximum time of t
. During this time, the status register and the RDY/BUSY pin will
EP
indicate that the part is busy.
If a sector is programmed or reprogrammed sequentially page by page, then the pro-
gramming algorithm shown in Figure 1 on page 29 is recommended. Otherwise, if
multiple bytes in a page or several pages are programmed randomly in a sector, then
the programming algorithm shown in Figure 2 on page 30 is recommended. Each page
within a sector must be updated/rewritten at least once within every 10,000 cumulative
page erase/program operations in that sector.
STATUS REGISTER READ: The status register can be used to determine the device’s
ready/busy status, or whether the sector protection has been enabled. To read the sta-
tus register, an opcode of D7H must be loaded into the device. After the opcode and
optional dummy byte is clocked in, the 1-byte status register will be clocked out on the
output pin (SO), starting with the next clock cycle. For applications over 25 MHz, the
opcode must be always followed with a dummy (don’t care) byte. The data in the status
register, starting with the MSB (bit 7), will be clocked out on the SO pin during the next
eight clock cycles.
The most-significant bits of the status register will contain device information, while the
remaining least-significant bit is reversed for future use and will have undefined value.
After the one byte of the status register has been clocked out, the sequence will repeat
itself (as long as CS remains low and SCK is being toggled). The data in the status reg-
ister is constantly updated, so each repeating sequence will output new data.
Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the
device is not busy and is ready to accept the next command. If bit 7 is a 0, then the
device is in a busy state. There are many operations that can cause the device to be in
a busy state: Main Memory Page to Buffer Transfer, Buffer to Main Memory Page Pro-
gram with Built-in Erase, Buffer to Main Memory Page Program without Built-in Erase,
Page Erase, Block Erase, Main Memory Page Program, and Auto Page Rewrite.
Bit 1 in the Status Register is used to provide information to the user whether or not the
sector protection has been enabled or disabled, either by software-controlled method or
hardware-controlled method. A logic 1 indicates that sector protection has been enabled
and logic 0 indicates that sector protection has been disabled.
The device density is indicated using bits 5, 4, 3, and 2 of the status register. For the
AT45DB321C, the four bits are 1,1, 0, 1. The decimal value of these four binary bits
does not equate to the device density; the four bits represent a combinational code
relating to differing densities of DataFlash devices. The device density is not the same
as the density code indicated in the JEDEC device ID information. The device density is
provided only for backward compatibility.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RDY/BUSY
X
1
1
0
1
Protect
X
7
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