AT45DB321C-RI ATMEL [ATMEL Corporation], AT45DB321C-RI Datasheet - Page 4

• Manufacturer Part Number: AT45DB321C-RI
• Description: 32 MEGABIT 2.7 VOLT DATAFLASH
• Manufacturer: ATMEL [ATMEL Corporation]

smaller density devices (see the notes under “Command Sequence for Read/Write
Operations (except Status Register Read)” on page 22. The next 13 bits (PA12-PA0) of
the 24-bit address sequence specify which page of the main memory array to read, and
the last 10 bits (BA9-BA0) of the 24-bit address sequence specify the starting byte
address within the page. The 32 don’t care clock cycles that follow the four address
bytes are needed to initialize the read operation. Following the don’t care clock cycles,
additional clock pulses on the SCK pin will result in data being output on the SO (serial
output) pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the
don’t care bytes, and the reading of data. When the end of a page in main memory is
reached during a Continuous Array Read, the device will continue reading at the begin-
ning of the next page with no delays incurred during the page boundary crossover (the
crossover from the end of one page to the beginning of the next page). When the last bit
in the main memory array has been read, the device will continue reading back at the
beginning of the first page of memory. As with crossing over page boundaries, no delays
will be incurred when wrapping around from the end of the array to the beginning of the
array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the
output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read
is defined by the f
specification. The Continuous Array Read bypasses both data
CAR
buffers and leaves the contents of the buffers unchanged.
MAIN MEMORY PAGE READ: A main memory page read allows the user to read data
directly from any one of the 8192 pages in the main memory, bypassing both of the data
buffers and leaving the contents of the buffers unchanged. To start a page read, an
opcode of D2H must be clocked into the device. The opcode is followed by three
address bytes (which comprise 24-bit page and byte address sequence) and 32 don’t
care clock cycles. The first bit of the 24-bit address sequence is a reserved bit, the next
13 bits (PA12-PA0) of the 24-bit address sequence specify the page in main memory to
be read, and the last 10 bits (BA9-BA0) of the 24-bit address sequence specify the start-
ing byte address within that page. The 32 don’t care clock cycles that follow the three
address bytes are sent to initialize the read operation. Following the don’t care bytes,
additional pulses on SCK result in data being output on the SO (serial output) pin. The
CS pin must remain low during the loading of the opcode, the address bytes, the don’t
care bytes, and the reading of data. When the end of a page in main memory is
reached, the device will continue reading back at the beginning of the same page. A
low-to-high transition on the CS pin will terminate the read operation and tri-state the
output pin (SO). The maximum SCK frequency allowable for the Main Memory Page
Read is defined by the f
specification. The Main Memory Page Read bypasses both
SCK
data buffers and leaves the contents of the buffers unchanged.
BUFFER READ: Data can be read from either one of the two buffers, using different
opcodes to specify which buffer to read from. An opcode of D4H is used to read data
from buffer 1, and an opcode of D6H is used to read data from buffer 2. To perform a
buffer read, the opcode must be clocked into the device followed by three address bytes
comprised of 14 don’t care bits and 10 buffer address bits (BFA9-BFA0). Following the
three address bytes, an additional don’t care byte must be clocked in to initialize the
read operation. Since the buffer size is 528 bytes, 10 buffer address bits are required to
specify the first byte of data to be read from the buffer. The CS pin must remain low dur-
ing the loading of the opcode, the address bytes, the don’t care bytes, and the reading
of data. When the end of a buffer is reached, the device will continue reading back at the
beginning of the buffer. A low-to-high transition on the CS pin will terminate the read
operation and tri-state the output pin (SO).
AT45DB321C [Preliminary]
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3387B–DFLSH–9/04