IS24C16 ISSI [Integrated Silicon Solution, Inc], IS24C16 Datasheet - Page 3

• Manufacturer Part Number: IS24C16
• Description: 16,384-BIT SERIAL ELECTRICALLY ERASABLE PROM
• Manufacturer: ISSI [Integrated Silicon Solution, Inc]

IS24C16
Acknowledge Polling
Once the internal write cycle has started and the
IS24C16 inputs are disabled, acknowledge polling can be
initiated. This involves sending a start condition followed
by the Device Addressing Byte. The read/write bit is
representive of the operation desired. Only if the internal
write cycle has been completed will the IS24C16 respond
with an acknowledge on the SDA bus allowing the read or
write sequence to continue.
READ OPERATION
READ operations are initiated in the same manner as
WRITE operations, except that the read/write bit of the
device addressing byte is set to “1”. There are three READ
operation options: current address read, random address
read and sequential read.
Current Address Read
The IS24C16 contains an internal address counter which
maintains the address of the last data word accessed,
incremented by one. For example, if the previous opera-
tion either a read or write operation addressed to the
address location n, the internal address counter would
increment to address location n+1. When the IS24C16
receives the Device Addressing Byte with a READ opera-
tion (read/write bit set to “1”), it will respond an ACKnowledge
and transmit the 8-bit data word stored at address location
n+1. If the Current Address READ operation only ac-
cesses a single byte of data, the master device terminates
the Current Address READ operation by pulling
ACKnowledge HIGH (lack of ACKnowledge) indicating the
last data word to be read, followed by a STOP condition.
(Refer to Figure 8. Current Address Read Diagram.)
Random Access Read
Random Address READ operation allows the master
device to access any memory location in a random fash-
ion. This operation involves a two-step process. First, the
master device generates a START condition and initiates
Device Addressing Byte with a WRITE operation (read/
write bit sets to “0”), followed by the address of the data
word the master device is to READ. This procedure stores
the desired address of data word to the internal address
counter of the IS24C16.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION
10/03/97
EE001-0C
After the data word address ACKnowledge is received by
the master device, the master device now initiates a
CURRENT ADDRESS READ by sending Device Ad-
dressing Byte with a READ operation (read/write bit sets to
“1”). The IS24C16 responds with an ACKnowledge and
transmits the eight data bits stored at the address location
where the master device is to READ. At this point, the
master device terminates the operation by pulling
ACKnowledge HIGH (lack of ACKnowledge) indicating the
last data word to be read, followed by a STOP condition.
(Refer to Figure 9. Random Address Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. The first data
word is transmitted as with the other byte read modes, the
master device now responds with an ACKnowledge indi-
cating that it requires additional data from the IS24C16.
The IS24C16 continues to output data for each
ACKnowledge received. the master device terminates the
sequential READ operation by pulling ACKnowledge HIGH
(lack of ACKnowledge) indicating the last data word to be
read, followed by a STOP condition.
The data output is sequential, with the data from
address n followed by the date from address n+1, ... etc.
The address counter increments by one automatically,
allowing the entire memory contents to be serially read
during sequential read operation. When the memory ad-
dress boundry (address 255) is reached, the address
counter “rolls over” to address 0, and the IS24C16 contin-
ues to output data for each ACKnowledge received. (Refer
to Figure 910. Sequential Read Operation Starting with a
Random Address READ Diagram.)
ISSI
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