CY14E256LA-ZS25XI CYPRESS [Cypress Semiconductor], CY14E256LA-ZS25XI Datasheet

no-image

CY14E256LA-ZS25XI

Manufacturer Part Number
CY14E256LA-ZS25XI
Description
256 Kbit (32K x 8) nvSRAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
Features
Cypress Semiconductor Corporation
Document Number: 001-54952 Rev. *B
25 ns and 45 ns Access Times
Internally Organized as 32K x 8 (CY14E256LA)
Hands off Automatic STORE on Power Down with only a Small
Capacitor
STORE to QuantumTrap Nonvolatile Elements Initiated by
Software, Device Pin, or AutoStore on Power Down
RECALL to SRAM Initiated by Software or Power Up
Infinite Read, Write, and Recall Cycles
1 Million STORE Cycles to QuantumTrap
20 year Data Retention
Single 5V +10% Operation
Industrial Temperature
44-Pin TSOP - II and 32-Pin SOIC Package
Pb-free and RoHS compliance
198 Champion Court
Functional Description
The Cypress CY14E256LA is a fast static RAM, with a nonvol-
atile element in each memory cell. The memory is organized as
32K bytes of 8 bits each. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power down. On power
up, data is restored to the SRAM (the RECALL operation) from
the nonvolatile memory. Both the STORE and RECALL opera-
tions are also available under software control.
256 Kbit (32K x 8) nvSRAM
San Jose
,
CA 95134-1709
Revised December 08, 2009
CY14E256LA
408-943-2600
[+] Feedback

Related parts for CY14E256LA-ZS25XI

CY14E256LA-ZS25XI Summary of contents

Page 1

... Document Number: 001-54952 Rev. *B 256 Kbit (32K x 8) nvSRAM Functional Description The Cypress CY14E256LA is a fast static RAM, with a nonvol- atile element in each memory cell. The memory is organized as 32K bytes of 8 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory ...

Page 2

... AC Switching Characteristics .........................................10 AutoStore/Power Up RECALL .........................................12 Software Controlled STORE/RECALL Cycle ..................13 Hardware STORE Cycle ...................................................14 Switching Waveforms ......................................................14 Truth Table For SRAM Operations ..................................15 Part Numbering Nomenclature ........................................15 Ordering Information ........................................................16 Package Diagram ..............................................................17 Document History Page ...................................................18 Sales, Solutions, and Legal Information ........................18 Worldwide Sales and Design Support .........................18 Products ......................................................................18 CY14E256LA Page 2 [+] Feedback ...

Page 3

... Address expansion for 4 Mbit. NC pin not connected to die. 4. Address expansion for 8 Mbit. NC pin not connected to die. 5. Address expansion for 16 Mbit. NC pin not connected to die. Document Number: 001-54952 Rev. *B [4] [3] [2] [1] [ Description CY14E256LA 32 - SOIC (x8) Top View (not to scale) Page 3 [+] Feedback ...

Page 4

... HSB goes LOW are inhibited until HSB pin, AutoStore returns HIGH. In case the write latch is not set, HSB is not driven CAP Preventing LOW by the CY14E256LA. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. CY14E256LA DC Electrical on page 8 for the size of V ...

Page 5

... L H Notes 6. While there are 15 address lines on the CY14E256LA, only the lower 14 are used to control software modes. 7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. Document Number: 001-54952 Rev. *B The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences ...

Page 6

... Output Data Output Data Output Data Output Data [7] Output Data Active I CC2 Output Data Output Data Output Data Output Data Output High-Z [7] Output Data Active Output Data Output Data Output Data Output Data Output High the CY14E256LA write mode Page 6 [+] Feedback ...

Page 7

... V value to make sure there is extra CAP store charge and store time should discuss their V selection with Cypress to understand any impact on the V voltage level at the end period. RECALL CY14E256LA value because CAP charge and CAP value. Customers CAP size ...

Page 8

... Max, V < V < Max, V < V < > OUT – pin and Rated CAP SS CY14E256LA + 2. 25°C) ....................................................1.0W Ambient Temperature V CC –40°C to +85°C 4.5V to 5.5V [8] Min Typ Max 4.5 5.0 5 STORE 5 –1 +1 – ...

Page 9

... (Typ Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. Figure 3. AC Test Loads 5.0V OUTPUT 512Ω CY14E256LA Min Unit 20 Years 1,000 K Max Unit 44-TSOP II 32-SOIC Unit °C/W 41 ...

Page 10

... HSB must remain HIGH during READ and WRITE cycles. Document Number: 001-54952 Rev Description Min [11, 12, 15 Address Valid t AA Output Data Valid t OHA CY14E256LA 45 ns Unit Max Min Max ...

Page 11

... WC Address Valid t SCE PWE Input Data Valid t t LZWE HZWE High Impedance [14, 15, 16 Address Valid SCE t PWE Input Data Valid High Impedance CY14E256LA [11, 15] t HZCE t HZOE Page 11 [+] Feedback ...

Page 12

... Figure 8. AutoStore or Power Up RECALL 18 t Note STORE t HHHD t LZHSB t DELAY t HRECALL Read & Write BROWN POWER-UP OUT RECALL AutoStore SWITCH. is below V CC SWITCH. Ω resistor, HSB driver is disabled. CY14E256LA CY14E256LA Min Max 4.4 150 1.9 5 500 [20 Note STORE 21 Note t HHHD t DELAY t LZHSB t HRECALL Read & ...

Page 13

... Note Figure 10. Autostore Enable / Disable Cycle t RC Address # HZCE Note Table 2 on page 5. WE must be HIGH during all six consecutive cycles. time. DELAY CY14E256LA Unit Max Min Max 200 200 [23 HHHD ...

Page 14

... HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven low DHSB DHSB [25, 26] Figure 12. Soft Sequence Processing t Soft Sequence SS Command Address #6 Address # CY14E256LA CY14E256LA Unit Min Max μs 100 t HHHD t LZHSB only by Internal Address #6 ...

Page 15

... Read 0 7 Output Disabled –DQ ); Write 0 7 Option Tape & Reel Blank - Std. Temperature Industrial (- Package TSOP SOIC Data Bus CY14E256LA Mode Power Standby Active Active Active o C) Speed Density: 256 - 256 Kb Page 15 [+] Feedback ...

Page 16

... Ordering Information Speed Ordering Code (ns) 25 CY14E256LA-ZS25XIT CY14E256LA-ZS25XI CY14E256LA-SZ25XIT CY14E256LA-SZ25XI 45 CY14E256LA-ZS45XIT CY14E256LA-ZS45XI CY14E256LA-SZ45XIT CY14E256LA-SZ45XI All the above parts are Pb-free. Document Number: 001-54952 Rev. *B Package Package Type Diagram 51-85087 44-pin TSOP II 51-85087 44-pin TSOP II 51-85127 32-pin SOIC 51-85127 32-pin SOIC 51-85087 ...

Page 17

... Package Diagram Document Number: 001-54952 Rev. *B Figure 13. 44-Pin TSOP II (51-85087) CY14E256LA 51-85087 *B Page 17 [+] Feedback ...

Page 18

... SEATING PLANE 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.026[0.660] 0.032[0.812] 0.004[0.101] 0.0100[0.254] CY14E256LA MIN. MAX. PART # S32.3 STANDARD PKG. SZ32.3 LEAD FREE PKG. 0.006[0.152] 0.021[0.533] 0.012[0.304] 0.041[1.041] 51-85127 *B Page 18 ...

Page 19

... Document History Page Document Title: CY14E256LA 256 Kbit (32K x 8) nvSRAM Document Number: 001-54952 Orig. of Submission Rev. ECN No. Change ** 2748216 GVCH/PYRS 08/04/2009 *A 2772059 GVCH 09/30/2009 *B 2829117 GVCH 12/16/09 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...

Related keywords