CY14B512J CYPRESS [Cypress Semiconductor], CY14B512J Datasheet
CY14B512J
Related parts for CY14B512J
CY14B512J Summary of contents
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... Restriction of hazardous substances (RoHS) compliant Overview The Cypress CY14C512J/CY14B512J/CY14E512J combines a 512-Kbit nvSRAM cell. The memory is organized words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory ...
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... Current nvSRAM Read .............................................. 12 Random Address Read ............................................. 13 Control Registers Slave ................................................. 14 Write Control Registers ............................................. 14 Current Control Registers Read ................................ 15 Random Control Registers Read .............................. 15 Document #: 001-65232 Rev. *B CY14B512J, CY14E512J Serial Number ................................................................. 16 Serial Number Write .................................................. 16 Serial Number Lock ................................................... 16 Serial Number Read .................................................. 16 Device ID ......................................................................... 17 Device ID Read ......................................................... 17 Executing Commands Using Command Register ....... 17 Best Practices ...
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... HSB 8 Description . SCL 2 C interface This pin is internally pulled LOW and hence can HHHD CY14C512J CY14B512J, CY14E512J CY14X512J2 Top View 6 3 SCL not to scale 5 4 SDA ) with standard output high current and then a ...
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... Repeated START condition to initiate a new operation max Pmin Pmax r b Vcc SDA CY14X512J #1 #0 CY14C512J CY14B512J, CY14E512J 2 C bus is acknowledged by the 2 C) nvSRAM OL Vcc CY14X512J #7 Page [+] Feedback ...
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... SDA pin and the master is free to generate a Repeated START or STOP condition. NACK can be generated by nvSRAM slave during a WRITE operation in following cases: ■ nvSRAM did not receive valid data due to noise. CY14C512J CY14B512J, CY14E512J SDA SCL P STOP Condition P Sr Acknowledgement ...
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... Figure 7. Data transfer format in Hs-mode Hs-mode A Sr SLAVE ADD DATA n (bytes + ack.) continue data transfer in Hs-mode, the master sends Repeated START (Sr). See Figure 16 on page 12 operation. CY14C512J CY14B512J, CY14E512J 8 9 clock pulse for acknowledgement F/S-mode Hs-mode continues SLAVE ADD. Sr Figure 13 on page 11 ...
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... LSB A0/X R/W 0x01 Serial Number 0x02 0x03 0x04 0x05 0x06 0x07 0x08 CY14C512J CY14B512J, CY14E512J Memory Slave Device on CY14X512J Slave Devices Memory × 8 Control Registers - Memory Control Register, 1 × Serial Number, 8 × Device ID, 4 × Command Register, 1 × 8 LSB ...
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... The Master sends Control Registers Slave device ID with I Write bit set (R/W = ’0’). 3. The Slave (nvSRAM) sends an ACK back to the Master. 4. The Master sends Command Register address (0xAA). 5. The Slave (nvSRAM) sends an ACK back to the Master. CY14C512J CY14B512J, CY14E512J Serial Number on page 16 for details on how to Command Description STORE ...
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... STORE sequence. DC Electrical A Power-Up RECALL cycle takes t . CAP memory access is disabled during this time. HSB pin can be used to detect the Ready status of the device. CY14C512J CY14B512J, CY14E512J Figure 10. AutoStore Mode CAP ...
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... More details on write instruction are provided in Section Slave Access on page 10. Document #: 001-65232 Rev. *B CY14B512J, CY14E512J Read Operation If the last bit of the slave device address is ‘1’, a read operation is assumed and the nvSRAM takes control of the SDA line immediately after the slave device address byte is sent out by the master ...
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... Address LSB A A Memory Slave Address Address MSB Address MSB Data Byte N Data Byte 3 A CY14C512J CY14B512J, CY14E512J Data Byte A Data Byte 1 Data Byte N A Address LSB Data Byte A A Address LSB Data Byte ...
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... Data Byte A A Data Byte A Memory Slave Address Memory Slave Address Data Byte A A CY14C512J CY14B512J, CY14E512J Read Operation on page 10 Data Byte ...
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... Address MSB Address LSB A A Address MSB Address LSB Address MSB CY14C512J CY14B512J, CY14E512J Memory slave Address Data Byte A Memory slave Address Data Byte 1 A Address LSB ...
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... In such a case, a following current read operation begins from the last acknowledged address. Control Register Address A A Control Register Address Data Byte A CY14C512J CY14B512J, CY14E512J Address LSB Memory Slave Address Data Byte 0 ...
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... Control Registers map (0x00 random read operation is initiated from an out-of-bound memory address, the nvSRAM sends a NACK after the address byte is sent. . Control Register Address Control Registers Slave Address CY14C512J CY14B512J, CY14E512J ...
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... Master may perform a serial number read operation to confirm if the correct serial number is written to the registers before setting the lock bit. CY14C512J CY14B512J, CY14E512J Data Byte A ...
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... The address latch of this slave for indicating the continues to point to the command register address. Command Register Address CY14C512J CY14B512J, CY14E512J bits) (3 bits) Density ID Die Rev 0011 000 0011 000 0011 000 0011 ...
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... Document #: 001-65232 Rev. *B CY14B512J, CY14E512J ■ Power-up boot firmware routines should rewrite the nvSRAM into the desired state (for example, AutoStore enabled). While the nvSRAM is shipped in a preset state, best practice is to ...
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... Supply voltage on V relative CY14C512J 2 2.6 V .....–0 +3 CY14B512J 2 3.6 V .....–0 +4 CY14E512J 4 5.5 V .....–0 +7 voltage applied to outputs in High Z state ..................................... –0 Input voltage ........................................ –0 ...
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... CY14B512J CY14E512J Description Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. and weak ( when the input voltage is above V IL CY14C512J CY14B512J, CY14E512J [3] Min Typ Max Unit 0.7 Vcc – 0 – 0.5 – ...
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... OUTPUT 100 pF AC Test Conditions Input pulse levels Input rise and fall times (10% - 90%) Input and output timing reference levels Document #: 001-65232 Rev. *B Figure 30. AC Test Loads and Waveforms For 3.0 V (CY14B512J) 3.0 V 867 OUTPUT 100 pF CY14C512J CY14B512J 2 ...
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... IL 0.3 – Figure 31. Timing Diagram t HD;STA SU;STA HIGH clock frequency (SCL) 100/400/1000 KHz; Cb < 100 pF for SCL at 3.4 MHz. CY14C512J CY14B512J, CY14E512J [7] [7] [7] 1 MHz 400 kHz Min Max Min Max – 1000 – 400 – 250 – 600 – ...
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... CY14B512J CY14E512J Figure 32. AutoStore or Power-Up RECALL 10 Note t t STORE HHHD t LZHSB t DELAY t FA Read & Write BROWN POWER-UP OUT RECALL AutoStore is below V CC SWITCH. CY14C512J CY14B512J, CY14E512J Min Max – 40 – 20 – 20 – 8 – 25 150 – – 2.35 – 2.65 – 4.40 – 5 – 1.9 – ...
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... Slave Figure 34. AutoStore Enable/Disable Cycle Command Reg Address Command Byte (ASENB/ASDISB) acknowledge (A) by Slave power must remain HIGH to effectively register command. CC CY14C512J CY14B512J, CY14E512J CY14X512J Unit Max 600 500 [16] acknowledge (A) by Slave STOP condition t / STORE ...
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... If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated. Document #: 001-65232 Rev. *B Min [17] Figure 35. Hardware STORE Cycle t STORE HSB pin is driven HIGH only by Internal 100 K resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven LOW. CY14C512J CY14B512J, CY14E512J CY14X512J Unit Max 15 – HHHD t LZHSB Page ...
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... SOIC (with V ) CAP Option Tape and Reel Blank - Std. Temperature Industrial (– Package 8-pin SOIC SF - 16-pin SOIC CAP and HSB Voltage 2 3 5.0 V CY14C512J CY14B512J, CY14E512J Operating Range Industrial C) ° Serial (I C) nvSRAM Density: 512 - 512 Kb Page [+] Feedback ...
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... Package Diagrams Figure 36. 8-pin (150 mil) SOIC Package, 51-85066 Document #: 001-65232 Rev. *B CY14C512J CY14B512J, CY14E512J 51-85066 *D Page [+] Feedback ...
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... Package Diagrams (continued) Document #: 001-65232 Rev. *B Figure 37. 16-pin (300 mil) SOIC, 51-85022 CY14C512J CY14B512J, CY14E512J 51-85022 *C Page [+] Feedback ...
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... Restriction of Hazardous Substances SNL Serial Number Lock SCL Serial Clock Line SDA Serial Data Line SOIC Small Outline Integrated Circuit WP Write protect Document #: 001-65232 Rev. *B CY14B512J, CY14E512J Document Conventions Units of Measure Symbol Unit of Measure °C degree Celsius Hz Hertz kbit 1024 bits kHz kilo Hertz k ...
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... Document History Page Document Title: CY14C512J, CY14B512J, CY14E512J, 512-Kbit (64 K × 8) Serial (I Document Number: 001-65232 Submission Rev. ECN No. Date ** 3089600 11/18/2010 *A 3201524 03/21/2011 *B 3248510 05/04/2011 Document #: 001-65232 Rev. *B Orig. of Description of Change Change GVCH New datasheet. GVCH Updated Configuration (Added Slave Address information). ...
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... Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-65232 Rev. *B All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised May 4, 2011 CY14C512J CY14B512J, CY14E512J PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...