LH28F160BGH-TL SHARP [Sharp Electrionic Components], LH28F160BGH-TL Datasheet - Page 11
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LH28F160BGH-TL
Manufacturer Part Number
LH28F160BGH-TL
Description
16 M-bit (1 MB x 16) Smart 3 Flash Memories
Manufacturer
SHARP [Sharp Electrionic Components]
Datasheet
1.LH28F160BGH-TL.pdf
(36 pages)
NOTES :
1. Bus operations are defined in Table 1.
2. X = Any valid address within the device.
3. SRD = Data read from status register. See Table 5 for a
4. Following the Read Identifier Codes command, read
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Word Write
Block Erase and
Word Write Suspend
Block Erase and
Word Write Resume
IA = Identifier code address : see Fig. 2.
BA = Address within the block being erased.
WA = Address of memory location to be written.
WD = Data to be written at location WA. Data is latched
ID = Data read from identifier codes.
operations access manufacture and device codes. See
Section 4.2 for read identifier code data.
COMMAND
on the rising edge of WE# or CE# (whichever
goes high first).
description of the status register bits.
BUS CYCLES
REQ
≥ 2
1
2
1
2
2
1
1
Table 2 Command Definitions
’
D.
NOTE
5, 6
4
5
5
5
Oper
- 11 -
Write
Write
Write
Write
Write
Write
Write
Write
(NOTE 1)
FIRST BUS CYCLE
5. If the block is boot block, WP# must be at V
6. Either 40H or 10H is recognized by the WSM as the
7. Commands other than those shown above are reserved
Addr
must be at V
operations. Attempts to issue a block erase or word write
to a boot block while WP# is V
word write setup.
by SHARP for future device implementations and should
not be used.
WA
BA
(NOTE 2)
X
X
X
X
X
X
(NOTE 7)
Data
40H or 10H
FFH
B0H
D0H
90H
70H
50H
20H
HH
(NOTE 3)
to enable block erase or word write
LH28F160BG-TL/BGH-TL
Oper
Read
Read
Write
Write
SECOND BUS CYCLE
(NOTE 1)
IH
or RP# is V
Addr
WA
BA
IA
(NOTE 2)
X
IH
Data
IH
.
SRD
D0H
WD
or RP#
ID
(NOTE 3)