M48Z12-150PC6 STMICROELECTRONICS [STMicroelectronics], M48Z12-150PC6 Datasheet - Page 3

• Manufacturer Part Number: M48Z12-150PC6
• Description: 16 Kbit 2Kb x 8 ZEROPOWER SRAM
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Figure 3. Block Diagram
READ MODE
The M48Z02/12 is in the Read Mode whenever W
(Write Enable) is high and E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 16,384 locations in the
static storage array. Thus, the unique address
specified by the 11 Address Inputs defines which
one of the 2,048 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (t
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before t
indeterminate state until t
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
Address Access.
ELQV
AXQX
AVQV
LITHIUM
) or Output Enable Access time (t
) but will go indeterminate until the next
CELL
, the data lines will be driven to an
AVQV
VOLTAGE SENSE
AVQV
. If the Address In-
SWITCHING
CIRCUITRY
AND
V CC
) after the last
GLQV
).
POWER
V PFD
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
C L includes JIG capacitance
DEVICE
UNDER
TEST
SRAM ARRAY
2K x 8
V SS
1k
M48Z02, M48Z12
5V
A0-A10
DQ0-DQ7
E
W
G
1.8k
AI01255
C L = 100pF
0V to 3V
1.5V
5ns
AI01019
OUT
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