M95M01-RMN6G STMICROELECTRONICS [STMicroelectronics], M95M01-RMN6G Datasheet - Page 18
M95M01-RMN6G
Manufacturer Part Number
M95M01-RMN6G
Description
1 Mbit serial SPI bus EEPROM with high speed clock
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.M95M01-RMN6G.pdf
(39 pages)
- Current page: 18 of 39
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Instructions
6.2
18/39
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven High.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
Figure 8.
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure
Write Disable (WRDI) sequence
S
C
D
Q
8, to send this instruction to the device, Chip Select (S) is driven Low,
High Impedance
0
1
2
Instruction
3
4
5
6
7
AI03750D
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