M24C32-R STMICROELECTRONICS [STMicroelectronics], M24C32-R Datasheet - Page 12

• Manufacturer Part Number: M24C32-R
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M24C64, M24C32
Figure 10. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
After the successful completion of a Read opera-
tion, the device’s internal address counter is incre-
mented by one, to point to the next byte address.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in
ure
Then, the bus master sends another Start condi-
tion, and repeats the Device Select Code, with the
Read/Write bit (RW) set to 1. The device acknowl-
edges this, and outputs the contents of the ad-
12/26
10.) but without sending a Stop condition.
CURRENT
ADDRESS
READ
RANDOM
ADDRESS
READ
SEQUENTIAL
CURRENT
READ
SEQUENTIAL
RANDOM
READ
DEV SEL *
DEV SEL *
DEV SEL
DEV SEL
ACK
DATA OUT N
R/W
R/W
R/W
ACK
ACK
ACK
ACK
R/W
NO ACK
DATA OUT 1
BYTE ADDR
BYTE ADDR
DATA OUT
Fig-
NO ACK
ACK
ACK
ACK
BYTE ADDR
BYTE ADDR
dressed
acknowledge the byte, and terminates the transfer
with a Stop condition.
Current Address Read
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the Read/Write bit (RW) set
to 1. The device acknowledges this, and outputs
the byte addressed by the internal address
counter. The counter is then incremented. The bus
master terminates the transfer with a Stop condi-
tion, as shown in
ing the byte.
ACK
ACK
ACK
byte.
DATA OUT N
DEV SEL *
DEV SEL *
st
Figure
The
and 4
NO ACK
R/W
ACK
ACK
R/W
th
bus
bytes) must be identical.
10., without acknowledg-
DATA OUT 1
DATA OUT
master
NO ACK
ACK
AI01105C
must
not