M95256-MN3/A STMICROELECTRONICS [STMicroelectronics], M95256-MN3/A Datasheet - Page 16

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M95256-MN3/A

Manufacturer Part Number
M95256-MN3/A
Description
256 Kbit Serial SPI bus EEPROM with high speed clock
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
M95256, M95128
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
Figure 11. Write Status Register (WRSR) Sequence
16/39
(BP1, BP0) bits of the Status Register, are
also hardware protected against data
modification.
by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
or by driving Write Protect (W) Low after
setting the Status Register Write Disable
(SRWD) bit.
S
C
D
Q
0
1
High Impedance
2
Instruction
3
4
5
6
7
MSB
7
8
6
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP1, BP0) bits of
the Status Register, can be used.
9 10 11 12 13 14 15
5
Register In
4
Status
3
2
1
0
AI02282D

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