M45PE10-VMN6G NUMONYX [Numonyx B.V], M45PE10-VMN6G Datasheet - Page 20
M45PE10-VMN6G
Manufacturer Part Number
M45PE10-VMN6G
Description
1-Mbit, page-erasable serial flash memory with byte-alterability and 75 MHz SPI bus interface
Manufacturer
NUMONYX [Numonyx B.V]
Datasheet
1.M45PE10-VMN6G.pdf
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Instructions
Figure 8.
1. The unique ID code is available only in the T9HX process (see
6.4
6.4.1
6.4.2
20/47
Read identification (RDID) instruction sequence and data-out sequence
Read status register (RDSR)
The read status register (RDSR) instruction allows the status register to be read. The status
register may be read at any time, even while a program, erase or write cycle is in progress.
When one of these cycles is in progress, it is recommended to check the write in progress
(WIP) bit before sending a new instruction to the device. It is also possible to read the status
register continuously, as shown in
The status bits of the status register are as follows:
WIP bit
The write in progress (WIP) bit indicates whether the memory is busy with a write, program
or erase cycle. When set to ‘1’, such a cycle is in progress, when reset to ‘0’ no such cycle is
in progress.
WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch. When
set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write enable latch is
reset and no write, program or erase instruction is accepted.
Table 5.
1. WEL and WIP are volatile read-only bits (WEL is set and reset by specific instructions; WIP is
automatically set and reset by the internal logic of the device).
b7
0
Status register format
0
0
Figure
0
Important note on page
9.
0
6).
0
WEL
(1)
M45PE10
WIP
b0
(1)
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