M95320-DW3G/P STMICROELECTRONICS [STMicroelectronics], M95320-DW3G/P Datasheet - Page 17
M95320-DW3G/P
Manufacturer Part Number
M95320-DW3G/P
Description
32 Kbit serial SPI bus EEPROMs with high-speed clock
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.M95320-DW3GP.pdf
(44 pages)
- Current page: 17 of 44
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M95320, M95320-W, M95320-R
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
●
●
●
●
Figure 8.
Power-up
WRDI instruction execution
WRSR instruction completion
WRITE instruction completion.
Figure
Write Disable (WRDI) sequence
S
C
D
Q
8, to send this instruction to the device, Chip Select (S) is driven low,
Doc ID 5711 Rev 12
High Impedance
0
1
2
Instruction
3
4
5
6
7
AI03750D
Instructions
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