M95320-R STMICROELECTRONICS [STMicroelectronics], M95320-R Datasheet - Page 7

• Manufacturer Part Number: M95320-R
• Description: 32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
Figure 4. Bus Master and Memory Devices on the SPI Bus
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SPI Interface with
(CPOL, CPHA) =
CS3
(0, 0) or (1, 1)
(ST6, ST7, ST9,
ST10, Others)
Bus Master
CS2
CS1
SDO
SDI
SCK
R
S
SPI Memory
C Q D
Device
W
HOLD
V
CC
R
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.
Figure 4.
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
S
SPI Memory
C Q D
Device
shows three devices, connected to an
W
HOLD
V
CC
R
S
M95640, M95320
SPI Memory
C Q D
Device
W
AI03746e
HOLD
V
CC
V
CC
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