M95128-R STMICROELECTRONICS [STMicroelectronics], M95128-R Datasheet - Page 12

• Manufacturer Part Number: M95128-R
• Description: 128 Kbit Serial SPI bus EEPROM with high speed clock
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Operating features
4.2
4.3
12/41
Status Register
Figure 3
Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see
Data Protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and
within applications that could experience problems if memory bytes are corrupted.
Consequently, the device features the following data protection mechanisms:
For any instruction to be accepted, and executed, Chip Select (S) must be driven High after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points need to be noted in the previous sentence:
Table 2.
Section 5.3: Read Status Register
Write and Write Status Register instructions are checked that they consist of a number
of clock pulses that is a multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-
only. This is the Software Protected Mode (SPM).
The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits to be protected.
This is the Hardware Protected Mode (HPM).
The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus
transaction for some other device on the SPI bus.
BP1
Status Register Bits
0
0
1
1
shows the position of the Status Register in the control logic of the device. The
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Write (WRITE) instruction completion
Write-Protected block size
BP0
0
1
0
1
Protected Block
Whole memory
Upper quarter
Upper half
(RDSR).
none
M95128, M95128-W, M95128-R
Array Addresses Protected
M95128, M95128-W, M95128-R
3000h - 3FFFh
2000h - 3FFFh
0000h - 3FFFh
none