M95010-BN3 STMICROELECTRONICS [STMicroelectronics], M95010-BN3 Datasheet - Page 7
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M95010-BN3
Manufacturer Part Number
M95010-BN3
Description
4Kbit, 2Kbit and 1Kbit Serial SPI Bus EEPROM With High Speed Clock
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
1.M95010-BN3.pdf
(37 pages)
CONNECTING TO THE SPI BUS
These devices are fully compatible with the SPI
protocol.
All instructions, addresses and input data bytes
are shifted in to the device, most significant bit
first. The Serial Data Input (D) is sampled on the
first rising edge of the Serial Clock (C) after Chip
Select (S) goes Low.
All output data bytes are shifted out of the device,
most significant bit first. The Serial Data Output
Figure 4. Bus Master and Memory Devices on the SPI Bus
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
SPI Interface with
(CPOL, CPHA) =
CS3
(0, 0) or (1, 1)
(ST6, ST7, ST9,
ST10, Others)
Bus Master
CS2
CS1
SDO
SDI
SCK
S
SPI Memory
C Q D
Device
W
HOLD
(Q) is latched on the first falling edge of the Serial
Clock (C) after the instruction (such as the Read
from Memory Array and Read Status Register in-
structions) have been clocked into the device.
Figure 4.
MCU, on a SPI bus. Only one device is selected at
a time, so only one device drives the Serial Data
Output (Q) line at a time, all the others being high
impedance.
S
SPI Memory
C Q D
shows three devices, connected to an
Device
W
HOLD
M95040, M95020, M95010
S
SPI Memory
C Q D
Device
W
AI03746D
HOLD
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