AT49LH00B4-33TC ATMEL [ATMEL Corporation], AT49LH00B4-33TC Datasheet - Page 16

• Manufacturer Part Number: AT49LH00B4-33TC
• Description: 4-megabit Top Boot, Bottom Partitioned Firmware Hub and Low-Pin Count Flash Memory
• Manufacturer: ATMEL [ATMEL Corporation]

Device Reset
Sector
Protection
Hardware Write
Protection
16
AT49LH00B4
Asserting RST or INIT initiates a device reset. In read mode, RST or INIT low deselects the
memory, places the output drivers in a high-impedance state, and turns off all internal circuits.
RST or INIT must be held low for the minimum specified t
operations). The device resets to read array mode upon return from reset, and all Sector Lock-
ing Registers are reset to their default (write-locked) state. Since all Sector Locking Registers
are reset, all sectors in the memory array are set to the write-locked status regardless of their
locked state prior to reset.
A reset recovery time (t
face) is required from RST or INIT switching back high until writes to the CUI are recognized.
A reset latency will occur if a reset procedure is performed during a programming or erase
operation.
During sector erase or program, driving RST or INIT low will abort the operation underway in
addition to causing a reset latency. Memory contents being altered are no longer valid since
the data may be partially erased or programmed.
It is important to assert RST or INIT during system reset. When the system comes out of reset,
it will expect to read from the memory array of the device. If a system reset occurs with no
FWH/LPC device reset (this will be hardware dependent), it is possible that proper CPU initial-
ization will not occur (the FWH/LPC memory may be providing status information instead of
memory array data).
Sectors in the memory array can be protected from program and erase operations using a
hardware controlled method and/or a software (register-based) controlled method.
Two pins are available to provide hardware write protection capabilities. The Top Boot Sector
Lock (TBL) pin, when held low, prevents program and sector erase operations to the top sec-
tor of the device (sector 10) where critical code can be stored.
When the TBL pin is high, hardware write protection for program and erase operations to the
top sector is disabled. Provided that the Write-Lock bits in the Sector Locking Registers are
not set (detailed later), sector erase or program commands can then be issued to the device to
erase the top 64-Kbyte sector (sector 10).
The Write Protect (WP) pin, which operates independently from the TBL pin, serves the same
basic function as the TBL pin for the remaining sectors except the top boot sector. When the
WP pin is held low, program and sector erase operations to sectors 9 through 0 will not be
allowed.
PHFV
using the FWH/LPC interface and t
PLPH
time (FWH/LPC and A/A Mux
PHAV
using the A/A Mux inter-
3379B–FLASH–9/03