AT88SC0204C-SU ATMEL [ATMEL Corporation], AT88SC0204C-SU Datasheet - Page 3

• Manufacturer Part Number: AT88SC0204C-SU
• Description: CryptoMemory 2 Kbit
• Manufacturer: ATMEL [ATMEL Corporation]

Reset (RST)
Serial Data (SDA/IO)
2022HS–SMEM–04/07
Table 2. DC Characteristics
Applicable over recommended operating range from V
Symbol
V
I
I
I
I
I
V
V
V
V
V
V
I
I
I
I
I
I
V
V
I
Note: 1. V
CC
CC
CC
CC
SB
IL
IL
IL
IH
IH
IH
OH
CC
IL
IL
IL
IH
IH
IH
OH
OL
Parameter
Supply Voltage
Supply Current (V
Supply Current (V
Supply Current (V
Supply Current (V
Standby Current (V
SDA/IO Input Low Threshold
SCL/CLK Input Low Threshold
RST Input Low Threshold
SDA/IO Input High Threshold
SCL/CLK Input High Threshold
RST Input High Threshold
SDA/IO Input Low Current
SCL/CLK Input Low Current
RST Input Low Current
SDA/IO Input High Current
SCL/CLK Input High Current
RST Input High Current
SDA/IO Output High Voltage
SDA/IO Output Low Voltage
SDA/IO Output High Current
IL
min and V
IH
max are reference only and are not tested.
CC
CC
CC
CC
CC
= 5.5V)
= 5.5V)
= 5.5V)
= 5.5V)
= 5.5V)
The AT88SC0204C provides an ISO 7816-3 compliant asynchronous answer to reset
sequence. When the reset sequence is activated, the device will output the data pro-
grammed into the 64-bit answer-to-reset register. An internal pull-up on the RST input
pad allows the device to be used in synchronous mode without bonding RST. The
AT88SC0204C does not support the synchronous answer-to-reset sequence.
The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and
may be wired with any number of other open drain or open collector devices. An exter-
nal pull-up resistor should be connected between SDA and V
resistor and the system capacitance loading the SDA bus will determine the rise time of
SDA. This rise time will determine the maximum frequency during read operations. Low
value pull-up resistors will allow higher frequency operations while drawing higher aver-
age power supply current. SDA/IO information applies to both asynchronous and
synchronous protocols.
When the synchronous protocol is used, the SCL/CLK input is used to positive edge
clock data into the device and negative edge clock data out of the device.
(1)
(1)
(1)
(1)
(1)
(1)
Test Condition
Async READ at 3.57MHz
Async WRITE at 3.57MHz
Synch READ at 1MHz
Synch WRITE at 1MHz
V
0 < V
0 < V
0 < V
V
V
V
20K ohm external pull-up
I
V
OL
OH
IN
CC
CC
CC
= 1mA
= V
x 0.7 < V
x 0.7 < V
x 0.7 < V
IL
IL
IL
CC
< V
< V
< V
CC
= +2.7 to 5.5V, T
or GND
CC
CC
CC
IH
IH
IH
x 0.15
x 0.15
x 0.15
< V
< V
< V
CC
CC
CC
AC
= -40
Min
V
V
V
V
CC
CC
CC
CC
o
2.7
C to +85
0
0
0
0
x 0.7
x 0.7
x 0.7
x 0.7
Typ
o
C (unless otherwise noted)
AT88SC0204C
Max
V
V
V
V
CC
CC
CC
CC
100
V
V
V
100
150
V
5.5
15
15
50
20
20
x 0.15
5
5
5
5
CC
CC
CC
CC
x 0.2
x 0.2
x 0.2
CC
. The value of this
Units
mA
mA
mA
mA
uA
uA
uA
uA
uA
uA
uA
uA
V
V
V
V
V
V
V
V
V
3