AT88SC0104CA-WI ATMEL [ATMEL Corporation], AT88SC0104CA-WI Datasheet - Page 6
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AT88SC0104CA-WI
Manufacturer Part Number
AT88SC0104CA-WI
Description
CryptoMemory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT88SC0104CA-WI.pdf
(20 pages)
7.2
Figure 7-1.
Figure 7-2.
Figure 7-3.
6
Memory Reset
AT88SC0104CA
Bus Time for 2-Wire Serial Communications. SCL: Serial Clock, SDA: Serial Data I/O
Write Cycle Timing. SCL: Serial Clock, SDA: Serial Data I/O
Data Validity
SDA
SCL
WORDn
After an interruption in communication due protocol errors, power loss or any reason, perform
"Acknowledge Polling" to properly recover from the condition. Acknowledge polling consists of
sending a start condition followed by a valid CryptoMemory command byte and determining if
the device responded with an ACKNOWLEDGE.
Note:
8th BIT
The Write Cycle time t
the internal clear/write cycle.
ACK
CONDITION
STOP
wr
is the time from a valid stop condition of a write sequence to the end of
ALLOWED
CHANGE
DATA
t
WR
(1)
CONDITION
START
5200AS–CRYPT–7/08