AT88SC0104CA-WI ATMEL [ATMEL Corporation], AT88SC0104CA-WI Datasheet - Page 5

• Manufacturer Part Number: AT88SC0104CA-WI
• Description: CryptoMemory
• Manufacturer: ATMEL [ATMEL Corporation]

Table 6-2.
Applicable over recommended operating range from V
7. Device Operations for Synchronous Protocols
7.1
7.1.1
7.1.2
7.1.3
5200AS–CRYPT–7/08
f
f
t
t
t
t
t
t
t
t
t
t
t
t
CLK
CLK
R
F
R
F
AA
HD.STA
SU.STA
HD.DAT
SU.DAT
SU.STO
DH
WR
Clock and Data Transitions
Start Condition
Stop Condition
ACKNOWLEDGE
Parameter
Async Clock Frequency
Synch Clock Frequency
Clock Duty cycle
“Rise Time - SDA/IO, RST”
“Fall Time - SDA/IO, RST”
Rise Time - SCL/CLK
Fall Time - SCL/CLK
Clock Low to Data Out Valid
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
AC Characteristics
The SDA pin is normally pulled high with an external device. Data on the SDA pin may change
only during SCL low time periods (see
periods will indicate a start or stop condition as defined below.
A high-to-low transition of SDA with SCL high defines a START condition which must precede all
commands (see
A low-to-high transition of SDA with SCL high defines a STOP condition. After a read sequence,
the STOP condition will place the EEPROM in a standby power mode (see
7).
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has received each word. This happens dur-
ing the ninth clock cycle (see
Figure 7-4 on page
CC
= +2.7 to 3.6V, T
Figure 7-5 on page
7).
AC
Figure 7-3 on page
= -40⋅C to +85⋅C, CL = 30pF (unless otherwise noted)
7).
Min
200
200
100
200
40
10
20
0
1
6). Data changes during SCL high
AT88SC0104CA
9% x period
9% x period
Max
250
60
4
1
1
1
5
Figure 7-4 on page
Units
MHz
MHz
mS
nS
nS
nS
uS
uS
uS
uS
nS
nS
nS
nS
%
5