AT24HC02B-10PU-1.8 ATMEL [ATMEL Corporation], AT24HC02B-10PU-1.8 Datasheet - Page 8

• Manufacturer Part Number: AT24HC02B-10PU-1.8
• Description: Utilizes Different Array Protection Compared
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 6. Output Acknowledge
Device Addressing
Write Operations
8
AT24HC02B
The 2K EEPROM device requires an 8-bit device address word following a start condi-
tion to enable the chip for a read or write operation, as shown in Figure 7.
Figure 7. Device Address
The device address word consists of a mandatory “1”, “0” sequence for the first four
most significant bits as shown. This is common to all the EEPROM devices.
The next three bits are the A2, A1 and A0 device address bits for the 2K EEPROM.
These three bits must compare to their corresponding hardwired input pins.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high, and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is
not made, the chip will return to a standby state.
BYTE WRITE: A write operation requires an 8-bit data word address following the
device address word and acknowledgement. Upon receipt of this address, the EEPROM
will again respond with a “0” and then clock in the first 8-bit data word. Following receipt
of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as
a microcontroller, must terminate the write sequence with a stop condition. At this time,
the EEPROM enters an internally-timed write cycle, t
inputs are disabled during this write cycle, and the EEPROM will not respond until the
write is complete, see Figure 8 on page 9.
2K
MSB
1
0
1
0
A
2
A
1
WR
A
, to the nonvolatile memory. All
0
R/W
LSB
5134A–SEEPR–9/05