93AA46/SM MICROCHIP [Microchip Technology], 93AA46/SM Datasheet - Page 11
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93AA46/SM
Manufacturer Part Number
93AA46/SM
Description
1K/2K/4K 1.8V Microwire Serial EEPROM
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.93AA46SM.pdf
(22 pages)
3.0
TABLE 3-1:
3.1
A high level selects the device. A low level deselects
the device and forces it into Standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought low during a program cycle, the
device will go into Standby mode as soon as the
programming cycle is completed.
CS must be low for 250 ns minimum (T
consecutive instructions. If CS is low, the internal
control logic is held in a Reset status.
3.2
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93AAXX.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
clock low time (T
freedom in preparing opcode, address and data.
CLK is a “don't care” if CS is low (device deselected). If
CS is high, but Start condition has not been detected,
any number of clock cycles can be received by the
device without changing its status (i.e., waiting for Start
condition).
CLK cycles are not required during the self-timed write
(i.e., auto erase/write) cycle.
2004 Microchip Technology Inc.
Name
ORG
CLK
V
V
DO
NU
CS
DI
CC
SS
PIN DESCRIPTION
Chip Select (CS)
Serial Clock (CLK)
CKL
PIN FUNCTION TABLE
Memory Configuration
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Not Utilized
Power Supply
). This gives the controlling master
Function
CSL
) between
CKH
) and
After detection of a Start condition the specified number
of clock cycles (respectively low-to-high transitions of
CLK) must be provided. These clock cycles are
required to clock in all required opcode, address and
data bits before an instruction is executed (see instruc-
tion set truth table). CLK and DI then become “don't
care” inputs waiting for a new Start condition to be
detected.
3.3
Data In is used to clock in a Start bit, opcode, address
and data synchronously with the CLK input.
3.4
Data Out is used in the Read mode to output data
synchronously with the CLK input (T
positive edge of CLK).
This pin also provides Ready/Busy status information
during erase and write cycles. Ready/Busy status infor-
mation is available on the DO pin if CS is brought high
after being low for minimum chip select low time (T
and an erase or write operation has been initiated.
The status signal is not available on DO, if CS is held
low or high during the entire write or erase cycle. In all
other cases DO is in the High-Z mode. If status is
checked after the write/erase cycle, a pull-up resistor
on DO is required to read the Ready signal.
3.5
When ORG is connected to V
organization is selected. When ORG is tied to V
(x8) memory organization is selected. ORG can only be
floated for clock speeds of 1MHz or less for the (x16)
memory organization. For clock speeds greater than 1
MHz, ORG must be tied to V
Note:
Data In (DI)
Data Out (DO)
Organization (ORG)
CS must go low between consecutive
instructions.
93AA46/56/66
CC
CC
or V
, the (x16) memory
SS
DS20067J-page 11
.
PD
after the
SS
, the
CSL
)