24AA256-EMC MICROCHIP [Microchip Technology], 24AA256-EMC Datasheet - Page 12

• Manufacturer Part Number: 24AA256-EMC
• Manufacturer: MICROCHIP [Microchip Technology]

24AAXX/24LCXX/24FCXX
5.5
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
FIGURE 5-1:
FIGURE 5-2:
DS21930B-page 12
SDA
SCL
Note:
SCL
SDA
(A)
Acknowledge
During a write cycle, the 24XX will not
acknowledge commands.
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Condition
Start
1
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
ACKNOWLEDGE TIMING
2
Data from transmitter
3
4
Acknowledge
Address or
Valid
(D)
5
6
to Change
Allowed
7
Data
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end-of-
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX) will leave the data line
high to enable the master to generate the Stop
condition (Figure 5-2).
Acknowledge
8
bit
9
(D)
1
Data from transmitter
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
2
© 2007 Microchip Technology Inc.
3
Condition
Stop
(C)
(A)