NLSX0102 ONSEMI [ON Semiconductor], NLSX0102 Datasheet - Page 9

• Manufacturer Part Number: NLSX0102
• Description: 2-Bit 20 Mb/s Dual-Supply Level Translator
• Manufacturer: ONSEMI [ON Semiconductor]

Level Translator Architecture
bi−directional voltage level shifting to transfer data in
multiple supply voltage systems. This device has two supply
voltages, V
and output sides of the translator. When used to transfer data
from the V
V
matched to V
translation shifts input signals with a logic level compatible
to V
that independently determine the direction of the data flow
without requiring a directional pin. The one−shot circuits are
used to detect the rising or falling input signals. In addition,
the one shots decrease the rise and fall time of the output
signal for high−to−low and low−to−high transitions. Each
input/output channel has an internal 10 kW pull−up. The
magnitude of the pull−up resistors can be reduced by
connecting external resistors in parallel to the internal 10 kW
resistors.
Input Driver Requirements
drain outputs depend on the magnitude of the pull−up
resistors. In addition, the propagation times (t
(t
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
ORDERING INFORMATION
NLSX0102FCT1G
NLSX0102FCT2G
Specifications Brochure, BRD8011/D.
PSKEW
L
The
The NLSX0102 consists of two bi−directional channels
The rise (t
supply are translated to output signals with a logic level
CC
to an output signal matched to V
) and maximum data rate depend on the impedance
NLSX0102
L
L
to the V
and V
R
) and fall (t
CC
. In a similar manner, the V
Device
CC
CC
, which set the logic levels on the input
ports, input signals referenced to the
auto
F
) timing parameters of the open
sense
translator
L
.
APPLICATIONS INFORMATION
PD
CC
provides
), skew
http://onsemi.com
to V
L
Flip−Chip 8
Flip−Chip 8
(Pb−Free)
(Pb−Free)
Package
9
of the device that is connected to the translator. The timing
parameters listed in the data sheet assume that the output
impedance of the drivers connected to the translator is less
than 50 kW.
Enable Input (EN)
tri−state operation at the I/O pins. Driving the Enable pin to
a low logic level minimizes the power consumption of the
device and drives the I/O V
impedance state. Normal translation operation occurs when
the EN pin is equal to a logic high signal. The EN pin is
referenced to the V
(OVT) protection.
Power Supply Guidelines
greater than, less than or equal to V
power supplies will not damage the device during the power
up operation. For optimal performance, 0.01 mF to 0.1 mF
decoupling capacitors should be used on the V
power supply pins. Ceramic capacitors are a good design
choice to filter and bypass any noise signals on the voltage
lines to the ground plane of the PCB. The noise immunity
will be maximized by placing the capacitors as close as
possible to the supply and ground pins, along with
minimizing the PCB connection traces.
The NLSX0102 has an Enable pin (EN) that provides
During normal operation, supply voltage V
L
supply and has Overvoltage Tolerant
CC
and I/O V
3000 / Tape & Reel
3000 / Tape & Reel
CC
Shipping
. The sequencing of the
L
pins to a high
†
L
L
and V
can be
CC