ADCMP580 AD [Analog Devices], ADCMP580 Datasheet

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ADCMP580

Manufacturer Part Number
ADCMP580
Description
Ultrafast SiGe Voltage Comparator
Manufacturer
AD [Analog Devices]
Datasheet
Preliminary Technical Data
FEATURES
150 ps propagation delay
25 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
100 ps minimum pulse width
35 ps typical output rise/fall
10 ps deterministic jitter(DJ)
200 fs random jitter (RJ)
−2 V to +3 V input range with +5 V/−5.2 V supplies
On-chip terminations at both input pinsl
Resistor-programmable hysteresis
Differential latch control
Power supply rejection > 70 dB
APPLICATIONS
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Clock and data signal restoration
GENERAL DESCRIPTION
The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage
comparators fabricated on Analog Devices, Inc. ’ s proprietary
XFCB3 Silicon Germanium (SiGe) bipolar process. The
ADCMP580 features CML output drivers; the ADCMP581
features reduced swing ECL (negative ECL) output drivers; and
the ADCMP582 features reduced-swing PECL (positive ECL)
output drivers.
The three comparators offer 150 ps propagation delay and 100
ps minimum pulse width for 10 Gbps operation with 200 fs
random jitter (RJ). Overdrive and slew rate dispersion is
typically less than 25 ps.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
ADCMP580/ADCMP581/ADCMP582
The ±5 V power supplies enable a wide −2 V to +3 V input
range with logic levels referenced to the CML/NECL/PECL
outputs. The three inputs have 50 Ω on-chip termination
resistors with the optional capability to be left open (on an
individual pin basis) for applications requiring high impedance
input.
The CML output stage is designed to directly drive 400 mV into
50 Ω transmission lines terminated to ground. The NECL
output stages are designed to directly drive 400 mV into 50 Ω
terminated to −2 V. The PECL output stages are designed to
directly drive 400 mV into 50 Ω terminated to V
speed latch and programmable hysteresis are also provided. The
differential latch input controls are also 50 Ω terminated to an
independent V
PECL logic.
The ADCMP580/ADCMP581/ADCMP582 are available in a
16-lead LFCSP package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
V
V
V
V
P
N
TN
TP
NONINVERTING
INVERTING
TERMINATION
TERMINATION
INPUT
INPUT
FUNCTIONAL BLOCK DIAGRAM
HYS
TT
pin to interface to either CML or ECL or to
ADCMP580/
ADCMP581/
ADCMP582
© 2004
© 2003 Analog Devices, Inc. All rights reserved.
Voltage Comparator
Figure 1.
LE INPUT
LE INPUT
Ultrafast SiGe
CML/ECL/
PECL
www.analog.com
CCO
− 2 V. High
Q OUTPUT
Q OUTPUT

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ADCMP580 Summary of contents

Page 1

... The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage comparators fabricated on Analog Devices, Inc. ’ s proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP580 features CML output drivers; the ADCMP581 features reduced swing ECL (negative ECL) output drivers; and the ADCMP582 features reduced-swing PECL (positive ECL) output drivers ...

Page 2

... Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Application Information.................................................................. 9 Power/Ground Layout and Bypassing ....................................... 9 ADCMP58x Family of Output Stages ....................................... 9 REVISION HISTORY 6/04—Revision PrA ADCMP580/ADCMP581/ADCMP582 Using/Disabling the Latch Feature..............................................9 Optimizing High Speed Performance ..................................... 10 Comparator Propagation Delay Dispersion ........................... 10 Comparator Hysteresis .............................................................. 11 Minimum Input Slew Rate Requirement ................................ 11 Typical Application Circuits.......................................................... 12 Timing Information ...

Page 3

... Input Resistance Input Resistance, Differential Mode Input Resistance, Common Mode Active Gain Common-Mode Rejection Hysteresis LATCH ENABLE CHARACTERISTICS ADCMP580 (CML) Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time ADCMP581 (NECL) Latch Enable Input Range Latch Enable Input Differential ...

Page 4

... Minimum Pulse Width Minimum Pulse Width Rise Time Fall Time POWER SUPPLY Positive Supply Voltage Negative Supply Voltage Logic Supply Voltage ADCMP580 (CML) Positive Supply Current Negative Supply Current Power Dissipation ADCMP581 (NECL) Positive Supply Current Negative Supply Current Power Dissipation ...

Page 5

... ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. THERMAL CONSIDERATIONS Rating The ADCMP580/ADCMP581/ADCMP582 LFCSP 16-lead package option has a θ −0 +6.0 V resistance) of 70°C/W in still air. –6 +0.5 V Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device ...

Page 6

... Termination Return Pin for the LE/LE Input Pins. TT For the ADCMP580 (CML output stage), this pin should be connected to the GND ground. For the ADCMP581 (ECL output stage), this pin should be connected to the –2 V termination potential. For the ADCMP582 (PECL output stage), this pin should be connected to the V ...

Page 7

... CCO Figure 5. Propagation Delay vs. Input Overdrive Figure 6. Propagation Delay vs. Input Common Mode Figure 7. Propagation Delay vs. Temperature = 25°C, unless otherwise noted. A Rev. PrA | Page ADCMP580/ADCMP581/ADCMP582 Figure 8. Rise/Fall Time vs. Temperature Figure 9. Hysteresis vs. R Control Resistor HYS Figure 10. Input Bias Current vs. Input Differential ...

Page 8

... Preliminary Technical Data Figure 11. Input Bias Current vs. Temperature Figure 12. Input Offset Voltages vs. Temperature ADCMP580/ADCMP581/ADCMP582 Figure 13. Output Levels vs. Temperature Rev. PrA | Page ...

Page 9

... Figure 14. Simplified Schematic Diagram of ADCMP580 CML Output Stage V and V EE, CCI, CCO ...

Page 10

... ADCMP58x family of comparators has almost equal delays for positive- and negative-going inputs. INPUT VOLTAGE Q/Q OUTPUT Figure 16. Propagation Delay—Overdrive Dispersion INPUT VOLTAGE Q/Q OUTPUT Figure 17. Propagation Delay—Slew Rate Dispersion Rev. PrA | Page ADCMP580/ADCMP581/ADCMP582 500mV OVERDRIVE 5mV OVERDRIVE V ± DISPERSION 1V/ns V ± ...

Page 11

... V/µs to ensure a clean output transition from the ADCMP58x family of comparators unless hysteresis is programmed as discussed previously. Rev. PrA | Page ADCMP580/ADCMP581/ADCMP582 – INPUT 0 OUTPUT Figure 18. Comparator Hysteresis Transfer Function of the ADCMP580/ADCMP581 Figure 19. Comparator Hysteresis vs. R Control Resistor HYS 1 ...

Page 12

... Q Q Rev. PrA | Page ADCMP580/ADCMP581/ADCMP582 GND 75Ω 75Ω 100Ω ADCMP580 100Ω 50Ω LATCH INPUTS ADCMP580 50Ω 50Ω 1.5kΩ Figure 23. Disabling the Latch Feature ADCMP580 HYS 50Ω 50Ω 0Ω TO 5kΩ Figure 25. Adding Hysteresis Using the HYS Control ...

Page 13

... Preliminary Technical Data TIMING INFORMATION Figure 26 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 4 provides a definition of the terms shown in the figure. LATCH ENABLE LATCH ENABLE DIFFERENTIAL INPUT VOLTAGE Q OUTPUT Q OUTPUT Table 4. Timing Descriptions Symbol Timing Description t Input to output high Propagation delay measured from the time the input signal crosses the reference (± the input offset ...

Page 14

... TYP 0.05 MAX 0.02 NOM 0.30 0.20 REF 0.23 0.18 * COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 27. 16-Lead Lead Frame Chip Scale Package [LFCSP] (CP-16) Dimensions shown in millimeters Package Description LFCSP-16 LFCSP-16 LFCSP-16 Rev. PrA | Page ADCMP580/ADCMP581/ADCMP582 0.50 0.40 0.30 PIN 1 INDICATOR 0.25 MIN Package Option CP-16 CP-16 CP-16 ...

Page 15

... Preliminary Technical Data NOTES ADCMP580/ADCMP581/ADCMP582 Rev. PrA | Page ...

Page 16

... Preliminary Technical Data NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR04672-0-6/04(PrA) ADCMP580/ADCMP581/ADCMP582 Rev. PrA | Page ...

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