ADCMP572BCP AD [Analog Devices], ADCMP572BCP Datasheet - Page 9

• Manufacturer Part Number: ADCMP572BCP
• Description: Ultrafast 3.3 V Single-Supply Comparators
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP572/ADCMP573 comparators are very high speed
SiGe devices. Consequently, it is essential to use proper high
speed design techniques to achieve the specified performance.
Of critical importance is the use of low impedance supply
planes, particularly the output supply plane (V
ground plane (GND). Individual supply planes are recom-
mended as part of a multilayer board. Providing the lowest
inductance return path for switching currents ensures the best
possible performance in the target application.
It is also important to adequately bypass the input and output
supplies. A 1 µF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.1 µF bypass capacitors should
be placed as close as possible to each of the V
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should also be strictly avoided to maximize
the effectiveness of the bypass at high frequencies.
If the input and output supplies are connected separately such
that V
these supplies separately to the GND plane. A bypass capacitor
should not be connected between them. It is recommended that
the GND plane separate the V
circuit board layout is designed to minimize coupling between
the two supplies and to take advantage of the additional bypass
capacitance from each respective supply to the ground plane.
This enhances the performance when split input/output supplies
are used. If the input and output supplies are connected
together for single-supply operation such that V
coupling between the two supplies is unavoidable; however,
every effort should be made to keep the supply plane adjacent
to the GND plane to maximize the additional bypass capacitance
this arrangement provides.
CML/RSPECL OUTPUT STAGE
Specified propagation delay dispersion performance can be
achieved only by using proper transmission line terminations.
The outputs of the ADCMP572 are designed to directly drive
400 mV into 50 Ω cable or microstrip and/or stripline transmis-
sion lines properly terminated to the V
CML output stage is shown in the simplified schematic diagram
of Figure 12. The outputs are each back-terminated with 50 Ω
for best transmission line matching. The RSPECL outputs of the
ADCMP573 are illustrated in Figure 13 and should be terminated
to V
tion networks may also be used in either case if the direct
termination voltage is not readily available. If high speed output
signals must be routed more than a centimeter, microstrip or
CCO
CCI
− 2 V. As an alternative, Thevenin equivalent termina-
≠
V
CCO
, then care should be taken to bypass each of
CCI
and V
CCO
CCO
supply plane. The
planes when the
CCI
CCO
and V
CCI
) and the
= V
CCO
CCO
, then
Rev. PrB | Page 9 of 16
stripline techniques are essential to ensure proper transition
times and to prevent output ringing and pulse-width dependant
propagation delay dispersion. For the most timing critical
applications where transmission line reflections pose the
greatest risk to performance, the ADCMP572 provides the best
match to 50 Ω output transmission paths.
USING/DISABLING THE LATCH FEATURE
The latch inputs (LE/ LE ) are active low for latch mode, and are
internally terminated with 50 Ω resistors to Pin 8. This
corresponds to the V
pin for the ADCMP573. All V
the supply plane for maximum performance, and the V
should be connected externally to V
own low inductance plane. When using the ADCMP572, the
latch function can be disabled by connecting the LE pin to
GND with an external pull-down resistor and leaving the LE
pin unconnected. To prevent excessive power dissipation, the
resistor should be 750 Ω when V
V
can be disabled by connecting the LE pin to V
CCO
= 5.2 V. When using the ADCMP573 comparator, the latch
Figure 12. Simplified Schematic Diagram of
Figure 13. Simplified Schematic Diagram of
the ADCMP573 RSPECL Output Stage
the ADCMP572 CML Output Stage
CCO
GND
supply for the ADCMP572 and the V
16mA
ADCMP572/ADCMP573
V
V
GND
CCO
CCO
CCO
CCO
pins should be connected to
50 Ω
CCO
= 3.3 V, and 1.2 kΩ when
– 2 V, preferably to its
Q
Q
CCO
Q
Q
with an
TT
pin
TT