CLC1018ISO8X CADEKA [Cadeka Microcircuits LLC.], CLC1018ISO8X Datasheet - Page 12

• Manufacturer Part Number: CLC1018ISO8X
• Description: 0.5mA, Low Cost, 2.5 to 5.5V, 75MHz Rail-to-Rail Amplifiers
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

Data Sheet
Table 1 provides the recommended R
loads. The recommended R
<1dB peaking in the frequency response. The Frequency
Response vs. C
of the CLCx008.
For a given load capacitance, adjust R
tradeoff between settling time and bandwidth. In general,
reducing R
additional overshoot and ringing.
Overdrive Recovery
An overdrive condition is defined as the point when either
one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLC1008, CLC1018, and CLC2008 will
typically recover in less than 20ns from an overdrive
condition. Figure 8 shows the CLC1008 in an overdriven
condition.
©2009-2011 CADEKA Microcircuits LLC
Input
Figure 7. Addition of R
C
100pF
10pF
20pF
50pF
L
(pF)
R
g
S
+
-
Table 1: Recommended R
will increase bandwidth at the expense of
L
R
plot, on page 4, illustrates the response
f
R
100
100
100
S
0
(Ω)
R
S
s
for Driving Capacitive Loads
S
values result in approximately
C
L
-3dB BW (kHz)
S
R
for various capacitive
L
S
10.2
22
19
12
vs. C
Output
S
to optimize the
L
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
▪
▪
▪
▪
▪
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
CEB002
CEB003
CEB006
CEB010
Evaluation Board
Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
Place the 6.8µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce
parasitic capacitance
Minimize all trace lengths to reduce series inductances
G = 5
Figure 8. Overdrive Recovery
Time (200ns/div)
#
Output
Input
CLC1008, CLC1018 in SOT23
CLC1008 in SOIC
CLC2008 in SOIC
CLC2008 in MSOP
Products
www.cadeka.com
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