OPA631N BURR-BROWN [Burr-Brown Corporation], OPA631N Datasheet - Page 16

• Manufacturer Part Number: OPA631N
• Description: Low Power, Single-Supply OPERATIONAL AMPLIFIERS TM
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

simply the specified no-load supply current times the total
supply voltage across the part. P
required output signal and load but would, for resistive load
connected to mid-supply (V
output is fixed at a voltage equal to V
condition, P
network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As a worst-case example, compute the maximum T
OPA632 (SOT23-6 package) in the circuit of Figure 1
operating at the maximum specified ambient temperature of
+85 C and driving a 150
P
Maximum T
Although this is still well below the specified maximum
junction temperature, system reliability considerations may
require lower guaranteed junction temperatures. The highest
possible internal dissipation will occur if the load requires
current to be forced into the output at high output voltages
or sourced from the output at low output voltages. This puts
a high current through a large internal voltage drop in the
output transistors.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA631 and OPA632 requires careful
attention to board layout parasitics and external component
types. Recommendations that will optimize performance
include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability: on the non-
inverting input, it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b) Minimize the distance (<0.25") from the power supply
pins to high frequency 0.1 F decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
connections should always be decoupled with these capaci-
tors. An optional supply decoupling capacitor (0.1 F) across
the two power supplies (for bipolar operation) will improve
2nd harmonic distortion performance. Larger (2.2 F to
6.8 F) decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may be
placed somewhat farther from the device and may be shared
among several devices in the same area of the PC board.
D
= 10V • 6.9mA + 5
DL
J
®
= +85 C + (0.08W • 150 C/W) = 97 C.
= V
OPA631, OPA632
S
2
/(16 • R
2
/(16 • (150
S
load at mid-supply.
/2), be at a maximum when the
L
), where R
DL
S
/4 or 3V
|| 1500 )) = 80mW
will depend on the
L
includes feedback
S
/4. Under this
J
using an
16
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance.
Resistors should be a very low reactance type. Surface-
mount resistors work best and allow a tighter overall layout.
Metal film or carbon composition axially-leaded resistors
can also provide good high frequency performance. Again,
keep their leads and PC board traces as short as possible.
Never use wirewound type resistors in a high frequency
application. Since the output pin and inverting input pin are
the most sensitive to parasitic capacitance, always position
the feedback and series output resistor, if any, as close as
possible to the output pin. Other network components, such
as non-inverting input termination resistors, should also be
placed close to the package. Where double-side component
mounting is allowed, place the feedback resistor directly
under the package on the other side of the board between the
output and inverting input pins. Even with a low parasitic
capacitance shunting the external resistors, excessively high
resistor values can create significant time constants that can
degrade performance. Good axial metal film or surface-
mount resistors have approximately 0.2pF in shunt with the
resistor. For resistor values > 1.5k , this parasitic capaci-
tance can add a pole and/or zero below 500MHz that can
effect circuit operation. Keep resistor values as low as
possible consistent with load driving considerations. The
750
tions is a good starting point for design. See Figure 4 for the
unity gain follower application.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set R
plot of Recommended R
capacitive loads (< 5pF) may not need an R
OPA631 and OPA632 are nominally compensated to oper-
ate with a 2pF parasitic load. Higher parasitic capacitive
loads without an R
(increasing the unloaded phase margin) If a long trace is
required, and the 6dB signal loss intrinsic to a doubly
terminated transmission line is acceptable, implement a
matched impedance transmission line using microstrip or
stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50 environ-
ment is normally not necessary on board, and in fact, a
higher impedance environment will improve distortion as
shown in the distortion versus load plots. With a character-
istic board trace impedance defined (based on board mate-
rial and trace dimensions), a matching series resistor into the
trace from the output of the OPA631 and OPA632 is used
as well as a terminating shunt resistor at the input of the
destination device. Remember also that the terminating
impedance will be the parallel combination of the shunt
resistor and the input impedance of the destination device;
this total effective impedance should be set to match the
trace impedance. If the 6dB attenuation of a doubly termi-
feedback used in the typical performance specifica-
S
are allowed as the signal gain increases
S
vs Capacitive Load. Low parasitic
S
S
since the
from the