ADA4841-X AD [Analog Devices], ADA4841-X Datasheet - Page 17

• Manufacturer Part Number: ADA4841-X
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
WITHOUT BUSY INDICATOR
This mode is usually used when the AD7689 is connected to an
SPI-compatible digital host. The connection diagram is shown
in Figure 17, and the corresponding timing is given in Figure
18.
A rising edge on CNV initiates a conversion and forces SDO to
high impedance. Once a conversion is initiated, it continues
until completion irrespective of the state of CNV. This could be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator.
Configuring the AD7689 for the (n + 1) conversion is initiated
when SCK is high and a rising edge on CNV. After this mode is
initiated, CNV is a don’t care as the CFG word is written in
MSB first with 14 SCK rising edges. As shown in Figure 18,
CFG is written to during the current (n) conversion before the
end of conversion, or t
ACQUISITION
(n)
CNV
SDO
SCK
DIN
CONV
t
CSCK
minimum time. At the end of
C13
1
t
SDIN
C12
CONVERSION
t
2
HDIN
(n)
t
C11
CNVH
Figure 18. Without Busy Indicator Serial Interface Timing
Figure 17. Without Busy Indicator Connection Diagram
3
t
CONV
AD7689
C1
CNV
SCK
13
SDO
C0
DIN
14
Rev. PrC | Page 17 of 20
t
conversion, the register is updated. In this mode, the new
configuration settings are used for the following (n + 1)
acquisition and conversion. The AD7689 can also be
configured on 14 SCKs of the data reading (not shown), thus
reducing the number of SCK bursts. However, this new CFG
setting is for the (n + 2) conversion since the (n) conversion has
ended. This mode is useful when using multiple AD7689s using
the same configuration.
When the conversion is complete, the AD7689 enters the
acquisition phase and powers down. When CNV goes low, the
MSB is output onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16
occurs first), SDO returns to high impedance.
EN
CLK
CONVERT
DATA IN
CFG DATA
DIGITAL HOST
t
th
CYC
SCK falling edge or when CNV goes high (whichever
D15
1
D14
2
t
HSDO
t
DSDO
D13
3
ACQUISITION
t
SCKH
14
(n + 1)
D2
t
ACQ
t
SCKL
15
D1
t
SCK
16
D0
t
DIS
AD7689
CONVERSION
(n + 1)