ADA4841-X AD [Analog Devices], ADA4841-X Datasheet - Page 16

• Manufacturer Part Number: ADA4841-X
• Manufacturer: AD [Analog Devices]

AD7689
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
For applications that use multiple AD7689s or other PulSAR
devices, it is more effective to use the internal reference buffer
to buffer the external reference voltage thus reducing SAR
conversion crosstalk.
The voltage reference temperature coefficient (TC) directly impacts
full scale; therefore, in applications where full-scale accuracy
matters, care must be taken with the TC. For instance, a
±15 ppm/°C TC of the reference changes full-scale by ±1 LSB/°C.
POWER SUPPLY
The AD7689 uses three power supply pins: two core supplies,
VDD, and a digital input/output interface supply, VIO. VIO
allows direct interface with any logic between 1.8 V and VDD.
To reduce the supplies needed, the VIO and VDD pins can be
tied together. The AD7689 is independent of power supply
sequencing between VIO and VDD. Additionally, it is very
insensitive to power supply variations over a wide frequency
range.
The AD7689 powers down automatically at the end of each
conversion phase; therefore, the operating currents and power
scale linearly with the sampling rate. This makes the part ideal
for low sampling rates (even of a few hertz) and low battery-
powered applications.
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7689, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 16. The reference line can be driven by
•
•
•
The system power supply directly
A reference voltage with enough current output capability,
such as the
A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 16
1
5V
OPTIONAL REFERENCE BUFFER AND FILTER.
10kΩ
1µF
Figure 16. Example of an Application Circuit
ADR43x/ADR44x
5V
AD8031
1
22µF
5V
CAP
10Ω
AD7689
VDD
1µF
VIO
Rev. PrC | Page 16 of 20
DIGITAL INTERFACE
The AD7689, uses a simple 4-wire interface and is compatible
with SPI, QSPI, digital hosts, and DSPs, for example, Blackfin®
ADSP-BF53x or ADSP-219x.
The interface uses the CNV, DIN, SCK, and SDO signals and
allows CNV, which initiates the conversions, to be independent
of the read back timing. This is useful in low jitter sampling or
simultaneous sampling applications.
CFG Writing
Prior to conversion, the AD7689 needs the CFG written to
unless the factory default setting is to be used as described in
the beginning of the Configuration Register section. If DIN is
high during the 1
the 14
disabled and not accept any new CFG data until after the end of
conversion, t
end of conversion for the setting to take effect for the next
conversion. It can also be updated while reading back data thus
minimizing the SCK activity.
Conversion Data
The conversion data can be read at any time; during acquisition,
during conversion and after conversion. While reading during
conversion, the data read is from the previous conversion (n-1)
as the current conversion (n) is active.
The AD7689 offers the flexibility to optionally force a start bit
in front of the data bits. This start bit can be used as a BUSY
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a BUSY indicator, the user must
time out the maximum conversion time prior to readback. The
BUSY indicator feature is enabled when the CNV is held low
before the maximum conversion time, t
Note that in the following sections, the timing diagrams
indicate digital activity (SCK, CNV, DIN) during the
conversion. However, due to the possibility of performance
degradation, digital activity should only occur prior to the
minimum conversion time, t
provides error correction circuitry that can correct for an
incorrect bit during this time. The user should configure the
AD7689 and initiate the busy indicator (if desired) during this
time. It is also possible to corrupt the sample by having SCK or
DIN transitions near the sampling instant. Therefore, it is
recommended to keep the digital pins quiet for approximately
30 ns before and 10 ns after the rising edge of CNV. To this
extent, it is recommended, to use a discontinuous SCK whenever
possible to avoid any potential performance degradation.
th
falling SCK edge. After the 14
CONV
st
(max). The CFG must be updated before the
SCK falling edge, CFG will be updated on
Preliminary Technical Data
CONV
(min) since the AD7689
th
SCK, the CFG will be
CONV
(max).