SA5225D PHILIPS [NXP Semiconductors], SA5225D Datasheet - Page 5

• Manufacturer Part Number: SA5225D
• Description: Fiber optic postamplifier
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
INPUT BIASING
The DATA INPUT pins (4 and 5) are DC biased at approximately
2.9V by an internal reference generator. The SA5225 can be DC
coupled, but the driving source must operate within the allowable
1.4V to 4.4V input signal range (for V
used to remove any DC compatibility requirement, the coupling
capacitors C1 and C2 must be large enough to pass the lowest input
frequency of interest. For example, .001 F coupling capacitors
react with the internal 4.5k input bias resistors to yield a lower –3dB
frequency of 35kHz. This then sets a limit on the maximum number
of consecutive “1”s or “0”s that can be sensed accurately at the
system data rate. Capacitor tolerance and resistor variation (2.9k to
7.6k) must be included for an accurate calculation.
AUTO-ZERO CIRCUIT
Figure 5 also shows the essential details of the auto-zero circuit. A
feedback amplifier (A4) is used to cancel the offset voltage of the
forward signal path, so the input to the internal ECL comparator (A6)
is at its toggle point in the absence of any input signal. The time
constant of the cancelling circuitry is set by an external capacitor
(C
–3dB frequency is:
where R
155k to 423k over temperature and device fabrication limits. The
input coupling time constant must also be considered in determining
the lower frequency response of the SA5225.
1998 Oct 07
AZ
Fiber optic postamplifier
) connected between Pins 1 and 2. The formula for the lower
AZ
Figure 3. Typical Fiber Optic Receiving System
is the internal driving impedance which can vary from
f
*3dB
NE5212
+
DATA IN
2p @ R
C2
C1
150
AZ
Figure 5. SA5225 Sample Application: Forward Gain Path Including Auto-Zero
@ C
NE5224
D
D
AZ
INB
IN
CC
R
4.5k
= 5V). If AC coupling is
IN
R
4.5k
IN
V
A1
BIAS
RECOVERY
RETIMING
CLOCK
&
SD00376
+
–
5
INPUT SIGNAL LEVEL-DETECTION
The SA5225 allows for user programmable input signal
level-detection and can automatically disable the switching of its
ECL data outputs if the input is below a set threshold. This prevents
the outputs from reacting to noise in the absence of a valid input
signal, and insures that data will only be transmitted when the input
signal-to-noise ratio is sufficient for low bit-error-rate system
operation. Complimentary ECL flags (ST and STB) indicate whether
the input signal is above or below the desired threshold level.
Figure 6 shows a simplified block diagram of the SA5225
level-detect system. The input signal is amplified and rectified
before being compared to a programmable reference. A filter is
included to prevent noise spikes from triggering the level-detector.
This filter has a nominal 1 s time constant, and additional filtering
can be achieved by using an external capacitor (CF) from Pin 7 to
V
resultant signal is then compared to a programmable level, V
which is set by an internal voltage reference (2.64V) and an external
resistor divider (R1 and R2). The value of R1 + R2 should be
maintained at approximately 5k.
The circuit is designed to operate accurately over a differential
2-12mV
V
Nominal hysteresis of 3dB is provided by the complimentary ECL
output comparator yielding
example, with V
input will drive the ST pin high, and an input level below 9.95mV
will drive the ST pin low.
Since a “JAM” function is provided (Pin 8) and can force the data
outputs to a predetermined state (D
ST and JAM pins can be connected together to automatically
disable signal transmission when the chip senses that the input
signal is below the desired threshold. JAM (Pin 8) low enables the
Data Outputs. ST will be in a high ECL state for input signals below
threshold.
CCA
SET
A3
/100, is the average of V
(the internal driving impedance is nominally 24k). The
C
250k
R
AZ
P-P
AZ
square-wave input level detect range. This level,
A4
SET
250k
R
= 1.2V, a 14.05mV
AZ
A6
D
D
V
OUT
OUTB
(OFF)
Figure 4.
TL
V
TH
TL
+
HYST
and V
OUT
V
121 and
(ON)
V
SET
TL
TH
P-P
= LOW, D
DATA OUT
.
ECL 10K
SD00668
square-wave differential
SD00377
V
Product specification
TH
OUT
SA5225
+
= HIGH), the
V
85 . For
SET
SET
P-P
,