HD6475328-CP10 HITACHI [Hitachi Semiconductor], HD6475328-CP10 Datasheet - Page 455

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HD6475328-CP10

Manufacturer Part Number
HD6475328-CP10
Description
original Hitachi CMOS microcomputer unit (MCU)
Manufacturer
HITACHI [Hitachi Semiconductor]
Datasheet
5. Mode 7
Figures E-9 and E-10 show how the pin states change when the RES pin goes Low in mode 7.
As soon as RES goes Low, all ports are initialized to the input (high-impedance) state.
The clock output pins P1
RES pin is sampled. Both pins are initialized to the output state.
ZTAT Versions
*
The dotted line indicates that P1
bit is 0, but clock output pins if the DDR bit is 1.
P1 / ø*
P1 / E*
RES
Internal reset signal
I/O ports
0
0
Figure E-9 Reset during Memory Access (Mode 7)
0
/ø and P1
1
/E are initialized 0.5 ø clock periods after the Low state of the
0
/ø and P1
0
/E are input port if the corresponding DDR
446
High impedance

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