74AHC377 PHILIPS [NXP Semiconductors], 74AHC377 Datasheet - Page 2

• Manufacturer Part Number: 74AHC377
• Description: Octal D-type flip-flop with data enable; positive-edge trigger
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
2000 Aug 15
t
f
C
C
PHL
max
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
Ideal for addressable register applications
Data enable for address and data synchronization
Eight positive-edge triggered D-type flip-flops
See “273” for master reset version
See “373” for transparent latch version
See “374” for 3-state version
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from 40 to +85 and from 40 to +125 C.
I
PD
Octal D-type flip-flop with data enable;
positive-edge trigger
P
f
f
C
V
i
o
/t
SYMBOL
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
(C
= output load capacitance in pF;
= C
is used to determine the dynamic power dissipation (P
= supply voltage in Volts.
L
PD
V
amb
CC
V
2
CC
= 25 C; t
f
2
o
propagation delay;
CP to Q
maximum clock frequency
input capacitance
power dissipation
capacitance
) = sum of outputs;
I
f
= GND to V
i
+
r
PARAMETER
= t
n
(C
f
L
3.0 ns.
CC
V
CC
.
2
CC
f
o
) where:
C
C
V
C
notes 1 and 2
I
L
L
L
= V
= 15 pF; V
= 15 pF; V
= 50 pF; f = 1 MHz;
CC
CONDITIONS
2
or GND
DESCRIPTION
The 74AHC/AHCT377 D-type flip-flops are high-speed
silicon-gate CMOS devices and are pin compatible with
low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT377 devices have eight edge-triggered,
D-type flip-flops with individual D inputs and Q outputs.
A common clock (CP) input loads all flip-flops
simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
The E input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
D
CC
CC
in W).
= 5 V
= 5 V
74AHC377; 74AHCT377
AHC
175
3.9
3.0
20
n
) of the flip-flop.
TYPICAL
Product specification
AHCT
140
4.0
3.0
23
ns
MHz
pF
pF
UNIT