SAK-XC161CJ-16F20F INFINEON [Infineon Technologies AG], SAK-XC161CJ-16F20F Datasheet - Page 5
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SAK-XC161CJ-16F20F
Manufacturer Part Number
SAK-XC161CJ-16F20F
Description
16-Bi t Single-Chip Microcontroller Preliminary
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.SAK-XC161CJ-16F20F.pdf
(78 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAK-XC161CJ-16F20F
Manufacturer:
BB
Quantity:
10
Preliminary
16-Bit Single-Chip Microcontroller
XC166 Family
XC161
1
• High Performance 16-bit CPU with 5-Stage Pipeline
• 16-Priority-Level Interrupt System with 74 Sources, Sample-Rate down to 50 ns
• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via
• Clock Generation via on-chip PLL (factors 1:0.15
• On-Chip Memory Modules
• On-Chip Peripheral Modules
• Idle, Sleep, and Power Down Modes with Flexible Power Management
• Programmable Watchdog Timer and Oscillator Watchdog
Data Sheet
– 25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle Multiplication (16
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 MBytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
via Prescaler (factors 1:1
– 2 KBytes On-Chip Dual-Port RAM (DPRAM)
– 4 KBytes On-Chip Data SRAM (DSRAM)
– 2 KBytes On-Chip Program/Data SRAM (PSRAM)
– 128 KBytes On-Chip Program Memory (Flash Memory)
– 12/16-Channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and
– Two 16-Channel General Purpose Capture/Compare Units (32 Input/Output Pins)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Two Synchronous/Asynchronous Serial Channels (USARTs)
– Two High-Speed-Synchronous Serial Channels
– On-Chip TwinCAN Interface (Rev. 2.0B active) with 32 Message Objects
– Serial Data Link Module (SDLM), compliant with J1850, supporting Class 2
– IIC Bus Interface (10-bit addressing, 400 kbit/s) with 3 Channels (multiplexed)
– On-Chip Real Time Clock, Driven by Dedicated Oscillator
Conversion Time (down to 2.85 s)
(Full CAN/Basic CAN) on Two CAN Nodes, and Gateway Functionality
Summary of Features
60:1)
16 bit), Background Division (32 / 16 bit) in 21 Cycles
1
1:10), or
V1.0, 2002-03
XC161