ZPSD211R-B-15J STMICROELECTRONICS [STMicroelectronics], ZPSD211R-B-15J Datasheet - Page 21

• Manufacturer Part Number: ZPSD211R-B-15J
• Description: Low Cost Field Programmable Microcontroller Peripherals
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

12.0
Control Signals
(Cont.)
18
PSD211R Family
Table 7B. Internal States During Power-down
NOTE: N/A = Not Applicable
12.6 Reset Input
This is an asynchronous input to initialize the PSD device.
Refer to tables 8A and 8B for information on device status during and after reset.
The standard-voltage PSD211R and ZPSD211R (non-V) devices require a reset input. In
this case, the reset input must be asserted for at least 100 nsec. The PSD will be functional
immediately after reset is de-asserted. For these standard-voltage devices, the polarity of
the reset input signal is programmable using PSDsoft (active-high or active-low), to match
the functionality of your MCU reset.
Note: It is not recommended to drive the reset input of the MCU and the reset input of the
PSD with a simple RC circuit between power on ground. The input threshold of the MCU
and the PSD devices may differ, causing the devices to enter and exit reset at different
times because of slow ramping of the signal. This may result in the PSD not being opera-
tional when accessed by the MCU. It is recommended to drive both devices actively. A
supervisory device or a gate with hysteresis is recommended.
For low-voltage ZPSD211RV devices only, the reset input must be asserted for at least
500 nsec. The ZPSD211RV will not be functional for an additional 500 nsec after reset is
de-asserted (see Figure 8). These low voltage ZPSD211RV devices require an active-low
polarity signal for reset. Unlike the PSD211R, the polarity of the reset input is not
programmable for the ZPSD211RV. If your MCU operates with an active high reset, you
must invert this signal before driving the ZPSD211RV reset input.
You must design your system to ensure that the PSD comes out of reset and the PSD
is active before the MCU makes its first access to PSD memory. Depending on the
characteristics and speed of your MCU, a delay between the PSD reset and the MCU reset
may be needed.
PAD A and PAD B
All registers in CSIOPORT address
space, including:
Direction
Data
PMR (turbo bit, ZPSD only)
Component
CS0–CS10
CSIOPORT, ES0–ES7
N/A
Internal Signal
Internal Signal State
During Power-Down
Logic 1 (inactive)
Logic 0 (inactive)
All unchanged