SAK-TC1197-256F180E INFINEON [Infineon Technologies AG], SAK-TC1197-256F180E Datasheet - Page 171

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SAK-TC1197-256F180E

Manufacturer Part Number
SAK-TC1197-256F180E
Description
32-Bit Single-Chip Microcontroller
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet

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SAK-TC1197-256F180E AC
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5) If the clock feedback is not enabled, the input signals are latched using the internal clock in the same way as
Figure 37
Data Sheet
BFCLKI
BFCLKO
A[23:0]
ADV
CS[3:0]
CSCOMB
RD
RD/WR
BAA
D[31:0]
(32-Bit)
D[15:0]
(16-Bit)
WAIT
at asynchronous access. So t5, t6, t7 and t8 from the asynchronous timings apply.
1)
1)
Output delays are always referenced to BCLKO. The reference clock for input
characteristics depends on bit EBU_BFCON.FDBKEN.
EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock.
EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock
t
t
t
22
EBU Burst Mode Read / Write Access Timing
10
21
Phase(s)
Address
t
25
t
22
t
t
12
26
Command
Phase(s)
feedback enabled).
Burst Start Address
t
22a
Phase(s)
167
Data (Addr+0)
Data (Addr+0)
Burst
t
23
t
24
Phase(s)
Burst
Data (Addr+4)
Data (Addr+2)
t
23
t
t
t
Electrical Parameters
22a
t
21
12
24
Recovery
Phase(s)
V1.1, 2009-05
BurstRDWR_4.vsd
t
t
t
Next Addr.
10
22
21
Phase(s)
TC1197
Next
Addr.

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