PXB4219E INFINEON [Infineon Technologies AG], PXB4219E Datasheet - Page 120
PXB4219E
Manufacturer Part Number
PXB4219E
Description
Interworking Element for 8 E1/T1 Lines
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.PXB4219E.pdf
(290 pages)
- Current page: 120 of 290
- Download datasheet (4Mb)
IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Memory Structure
The external RAM is organized as a 64k x 32 bit parity protected memory.
Accesses to internal configuration RAM’s or external RAM are always 32 bit oriented.
6.1
Internal Configuration RAM’s
The 4 internal 256 x 32 bit configuration RAM’s (RAM1, RAM2, RAM3 and RAM4) are
used to assign the timeslots of the Framer Receive and Framer Transmit interfaces to
ATM channels. For each port there are 32 entries. RAM1 is used to define the timeslots
of the Framer Receive ports, and RAM2 and RAM3 are used to define the Framer
Transmit ports. RAM4 is responsible for CAS conditioning and freezing in transmit
direction
When the contents of the internal RAMs have been altered by the software, the internal
state machines will load the new values within the next 1.5 frame cycles (187.5 µs). Up
to that point of time the previous values are used.
Data Sheet
120
2003-01-20
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