SSTUM32868ET/G NXP [NXP Semiconductors], SSTUM32868ET/G Datasheet - Page 23
SSTUM32868ET/G
Manufacturer Part Number
SSTUM32868ET/G
Description
1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
Manufacturer
NXP [NXP Semiconductors]
Datasheet
1.SSTUM32868ETG.pdf
(30 pages)
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NXP Semiconductors
SSTUM32868_2
Product data sheet
11.3 Error output load circuit and voltage measurement
V
All input pulses are supplied by generators having the following characteristics:
PRR
Fig 19. Load circuit, error output measurements
Fig 20. Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to
Fig 21. Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect
DD
= 1.8 V
(1) C
10 MHz; Z
RESET input
to clock inputs
L
includes probe and jig capacitance.
0.1 V.
0
waveform 1
= 50 ; input slew rate = 1 V/ns
waveform 2
RESET
output
timing
inputs
output
Rev. 02 — 2 March 2007
LVCMOS
1.8 V DDR2-800 configurable registered buffer with parity
t
DUT
PLH
OUT
t
V
PHL
0.5V
ICR
0.15 V
DD
0.5V
DD
C
L
= 10 pF
V
ICR
(1)
20 %, unless otherwise specified.
V
DD
R
test point
002aaa500
L
002aab904
= 1 k
002aab903
SSTUM32868
V
V
V
V
0 V
V
0 V
DD
OL
i(p-p)
DD
OH
© NXP B.V. 2007. All rights reserved.
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