ADUC842BCP AD [Analog Devices], ADUC842BCP Datasheet - Page 16

• Manufacturer Part Number: ADUC842BCP
• Description: 12- Bit ADCs and DACs with Embedded Hi-Speed 62KB FLASH MCU
• Manufacturer: AD [Analog Devices]

The main features of the MicroConverter I
Software Master Mode
The ADuC841 can be used as a I
uring the I
to output the data bit by bit. This is referred to as a software
master. Master mode is enabled by setting the I2CM bit in
the I2CCON register.
To transmit data on the SDATA line, MDE must be set to
enable the output driver on the SDATA pin. If MDE is set
then the SDATA pin will be pulled high or low depending
on whether the MDO bit is set or cleared. MCO controls the
SCLOCK pin and is always configured as an output in mas-
ter mode. In master mode the SCLOCK pin will be pulled
high or low depending on the whether MCO is set or
cleared.
To receive data, MDE must be cleared to disable the output
driver on SDATA. Software must provide the clocks by tog-
gling the MCO bit and read SDATA pin via the MDI bit. If
MDE is cleared MDI can be used to read the SDATA pin.
The value of the SDATA pin is latched into MDI on a rising
edge pf SCLOCK. MDI is set if the SDATA pin was high
on the last rising edge of SCLOCK. MDI is clear if the
SDATA pin was low on the last rising edge of SCLOCK.
Software must control MDO, MCO and MDE appropri-
ately to generate the START condition, slave address,
ADuC842
- Only two bus lines are required; a serial data line
- An I
- Ability to respond to 4 seperate addresses when operat-
- An I
- On-Chip filtering rejects <50ns spikes on the SDATA
(SDATA) and a serial clock line (SCLOCK).
devices. Because each slave device has a unique 7-bit
address then single master/slave relationships can exist
at all times even in a multi slave environment
ing in slave mode
without a stop bit in between. This allows a master to
change direction of transfer without giving up the bus.
and the SCLOCK lines to preserve data integrity.
2
2
C slave can respond to repeated start conditions
2
C master can communicate with multiple slave
C peripheral in master mode and writing sotware
MA STER
Figure 36. Typical I
I
2
C
DV
DD
2
C master device by config-
2
C System
SLAVE#1
SLAVE#2
I
I
2
2
C
C
2
C interface are:
–16–
acknowledge bits, data bytes and STOP conditions appro-
priately. These functions are provided in tech note uC001.
Hardware Slave Mode
After reset the ADuC842 defaults to hardware slave mode.
The I
SPICON. Slave mode is enabled by clearing the I2CM bit
in I2CCON. The ADuC842 has a full hardware slave. In
slave mode the I
ter. Data received or to be transmitted is stored in the
I2CDAT register.
Once enabled in I
a START condition. If the ADuC842 detects a valid start
condition, followed by a valid address, followed by the R/W
bit the I2CI interrupt bit will get automatically set by hard-
ware.
The I
user has pre-configured the I
IEIP2 SFR as well as the global interrupt bit EA in the IE
SFR. i.e.
On the ADuC841 an auto-clear of the I2CI bit is imple-
mented so this bit is cleared automatically on a read or write
access to the I2CDAT SFR.
If for any reason the user tries to clear the interrupt more
than once i.e. access the data SFR more than once per inter-
rupt then the I
have to be reset using the I2CRS bit.
The user can choose to poll the I2CI bit or enable the inter-
rupt. In the case of the interrupt the PC counter will vector
to 003BH at the end of each complete byte. For the first byte
when the user gets to the I2CI ISR the 7-bit address and the
R/W bit will appear in the I2CDAT SFR.
The I2CTX bit contains the R/W bit sent from the master.
If I2CTX is set then the master would like to receive a byte.
Hence the slave will transmit data by writing to the I2CDAT
register. If I2CTX is cleared the master would like to trans-
mit a byte. Hence the slave will receive a serial byte.
Software can interrogate the state of I2CTX to determine
whether is should write to or read from I2CDAT.
Once the ADuC842 has received a valid address, hardware
will hold SCLOCK low until the I2CI bit is cleared by soft-
ware. This allows the master to wait for the slave to be ready
before transmitting the clocks for the next byte.
The I2CI interrupt bit will be set every time a complete data
byte is received or transmitted provided it is followed by a
valid ACK. If the byte is followed by a NACK an interrupt is
NOT generated. The ADuC842 will continue to issue inter-
rupts for each complete data byte transferred until a STOP
condition is received or the interface is reset.
When a STOP condition is received, the interface will reset
to a state where it is waiting to be addressed (idle). Simi-
larly, if the interface receives a NACK at the end of a
sequence it also returns to the default idle state. The I2CRS
bit can be used to reset the I
used to force the interface back to the default idle state.
;
MOV
SETB
MOV
MOV
2
2
Enabling
C interface is enabled by clearing the SPE bit in
C peripheral will only generate a core interrupt if the
EA
IEIP2,#01h
2
C controller will halt. The interface will then
I2CDAT, A
A, I2CDAT
2
C address is stored in the I2CADD regis-
2
I2C
C slave mode the slave controller waits for
Interrupts
2
2
C interrupt enable bit in the
C interface. This bit can be
; enable I2C interrupt
; I2CI auto-cleared
; I2CI auto-cleared
for
the
Rev.PrB
ADuC831