ADUC842BCP AD [Analog Devices], ADUC842BCP Datasheet - Page 14

• Manufacturer Part Number: ADUC842BCP
• Description: 12- Bit ADCs and DACs with Embedded Hi-Speed 62KB FLASH MCU
• Manufacturer: AD [Analog Devices]

I
The ADuC842 supports a fully licensed
The I
and software master. SDATA is the data I/O pin and
SCLOCK is the serial clock. These two pins are shared with
the MOSI and SCLOCK pins of the on-chip SPI interface.
ADuC842
Three SFRs are used to control the I
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
2
C-COMPATIBLE INTERFACE
I2CCON:
SFR Address
Power-On Default Value
Bit Addressable
2
C interface is implemented as a full hardware slave
M D O
M D E
M C O
M D I
I2CM
----
----
----
I2CSI
I2CGC
I2CID1
I2CID0
I2CM
I2CRS
I2CTX
Name
I
This data bit is used to implement a master I
to this bit will be outputted on the SDATA pin if the data output enable (MDE) bit is set.
I
Set by user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable SDATA pin as an input (Rx).
I
This data bit is used to implement a master I
written to this bit will be outputted on the SCLOCK pin.
I
This data bit is used to implement a master I
SDATA pin is latched into this bit on SCLOCK if the Data Output Enable (MDE) bit is ‘0.’
I
Set by user to enable I
Cleared by user to enable I
RSVD
RSVD
RSVD
Table I2CCON SFR Bit Designations Slave Mode
Name
I
Set by the user to enable I2C stop interrupts. If set a stop bit that follows a valid start
condition will generate an interrupt.
Cleared by the user to disable I2C stop interrupts.
I
Set by hardware after receiving a general call address.
Cleared by the user.
I
Set by hardware to indicate the source of an I2C interrupt
00 Start and Matching Address
01 Repeated Start and Matching Address
10 User Data
11 Stop after a Start and Matching Address
I
Set by user to enable I
Cleared by user to enable I
I
Set by user to reset the I
Cleared by user code for normal I
I
Set by the MicroConverter if the interface is transmitting.
2
2
2
2
2
2
2
2
2
2
2
C Software Master Data Output Bit (MASTER MODE ONLY).
C Software Master Data Output Enable Bit (MASTER MODE ONLY).
C Software Master Clock Output Bit (MASTER MODE ONLY).
C Software Master Data Input Bit (MASTER MODE ONLY).
C Master/Slave Mode Bit.
C Stop Interrupt Enable Bit.
C General Call Status Bit
C Interrupt Decode Bits.
C Master/Slave Mode Bit.
C Reset Bit (SLAVE MODE ONLY).
C Direction Transfer Bit (SLAVE MODE ONLY).
I
E8H
00H
Yes
2
Table I2CCON SFR Bit Designations Master Mode
C Control Register
*
2
C interface. These are described below:
I
2
C serial interface.
2
2
C software master mode.
C software master mode.
2
Description
Description
C interface.
2
2
–14–
C hardware slave mode.
C hardware slave mode.
To enable the I2C interface the SPI interface must be turned
off (see SPE in SPICON previously) OR the SPI interface
must be moved to P3.3, P3.4 and P3.5 via the CFG841.1
bit. Application Note uC001 describes the operation of this
interface as implemented is available from the
MicroConverter Website at www.analog.com/
microconverter.
2
C operation.
2
2
C transmitter interface in software. Data written
C receiver interface in software. Data on the
2
C transmitter interface in software. Data
Rev.PrB